LMK04806: SYNC function

Hello Christopher,
let me check your sequence and come back to you.
To complete the picture of your observation - can you please let me know which outputs and which inputs you observed? Do you use the TI EVM or are you already in prototyping phase of your own PCB?

Best regards,
Patrick

Patrick,

We are using the CLKOUT2-5 outputs to provide the 30.720 MHz reference clocks to 4 Analog Device AD9361 radio ICs on our custom board.  This board has been working for the last couple years.  I just recently modified the FPGA logic to use the SYNC function and modified the LMK04806 programming accordingly.

What I found is that the single change to the SYNC_QUAL bit setting will break the system.  Specifically, it will cause one of the radio ICs to fail its initialization.  While I have not verified this, I suspect the most likely cause is that the reference clock for that chip is not at the right frequency, or not running.

Chris Y

Hello Christopher,

I checked the config and checked it on an EVM. So on the EVM I see the expected behaviour. I'm not sure at this point what will cause an issue for your system. Therefore let me try to describe what happens:

Sync

Sync happens with respect to the clock tree or VCO frequency. As the internal delay from SYNC pin to the point of synchronization at the VCO can vary, you will see deterministic behaviour of all outputs being reset at the same VCO cycle, but with respect to OSCin (which has a lower frequency) you are likely to see the phase varying in a grid of VCO cycles. The SYNC signal provided to the pin acts upon the polarity and the rising and falling edge respectively. E.g. in your config the SYNC is driven to LOW level, all outputs (except the ones with NO_SYNC) will become mute. The "low pulse width" of the SYNC determines relates to the mute time of the outputs. Hence the longer the SYNC is low, the longer the outputs are muted.

Qualified Sync

In this mode the phase ambiguity of SYNC is overcome by selecting a specific VCO period internally. Therefore the potential variation of the propagation delay from the SYNC signal to the point of synchronization at the clock distribution is not dominating anymore. The feedback mux is re-used to choose an output clock (falling edge) to determine a specific VCO cycle where to start the divider synchronization. The actual synchronization is very quick, therefore to be able to see it on a scope it is very likely that you have to use the digital delay feature to create an artificial mute to be able to see that the SYNC happens. The SYNC signal you provide to the pin is also not interpreted anymore with respect to the "low pulse width" (=mute time). The device will only look at the next rising edge (in your config) to trigger the SYNC event. As the VCO cycle is qualified using a specific output clock, that clock has the no_sync bit set to avoid that sync itself again (=blocks itselfs).

My suspision is that you may have to adapt the SYNC signal and the timing when the system clock is assumed to be ready.

Furthermore the no_sync set in the former "qualification channel" could lead to this output clock becoming delayed to the other outputs. Maybe this impacts your system?

May I ask which change triggered to update the config in the system and changing the working scheme? Maybe we have to reflect that update in the relative timings as the device is going to behave slightly different?

From my EVM test: CLKout0 (CH1) and CLKout4 (re-configured to LVDS to fit my EVM on CH2) and CLKout4_5_DDLY=63 to show the mute gap from the SYNC event.

Best regards,

Patrick