• State Resolved
  • Locked Locked
  • Replies 5 replies
  • Answers 2 answers
  • Subscribers 22 subscribers
  • Views 850 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

LMX2485E: LMX2485E: About sensitivity in RF input

user277644
Prodigy 120 points
Part Number: LMX2485E

Hello, 

LMX2485E is used to synthetize the frequency range from 750 MHz to 780MHz. To reduce the spurs level, I have checked that when the isolation between FinRF pin (LMX2485E) and VCO RF output is increased, the spurs level is improved several dBs, therefore I think that this could be crosstalk spurs.

My question is related to the sensitivity of  FinRF (LMX2485E) for the operation frequencies mentioned above. When the isolation is increased to reduce spurs, then the RF level in the input of PLL is reduced. 

Currently, the RF level is about -18dBm to the input of PLL. In data sheet , a minimum level of -15dBm is required for all frequency ranges and temperatures, but revising the graphics included in datasheet, for our frequency range a minimum level of -30dBm is indicated for a 16 prescaler (RF_P=1). 

We are using a RF_P=0 (Prescaler=8) in our design, is the RF sensitivity to the input of PLL similar than for RF_P=1 (16 prescaler) ? Is a -18dBm input level right or is it necessary to increase it?

On the other hand, I have checked the performance of PLL for RF input levels about -25 dBm and all looks like OK at 25ºC

Thanks in advance.

  • 0
    TI__Expert 5325 points
    Hello user277644,
    an expert for this device will reply to your question!

    Best regards,
    Patrick
  • 0 in reply to Patrick Kammermayer
    TI__Guru** 108330 points
    Hi There,

    The graphics show the typical performance at some particular condition while the data in the electrical table is what we can guarantee over PVT. So to play safe, please follow the suggestion in the electrical table.
    What is your configuration and what spurs did you see? Let's see if we can provide some suggestions to overcome the spurs issue in a different way.
  • 0 in reply to Noel Fung
    Prodigy 120 points

    Thank you for your response.

    PLL configuration is shown in the following figure:

    The spurs are the primary fractional. Channels frequencies can be each 6.25 KHz. Primary fractionals are 6.25KHz, 12.5KHz,25KHz and 31.25 KHz.

    The way to connect VCO to PLL is show as follows:

    It is observed that if R2 is increased , for example 1Kohms, fractional spurs are reduced more than 5dB although PLL input level  is reduced , too. Due to this effect, I think that could be crosstalk as indicated in AN-1879 Application Note.

    Input level for PLL is calculated in simulation using the input impedance (vs. frequency) included in data sheet.

    RF output level for VCO is about +3 dBm.

    Could these primary fractional spurs be reduced in another way? In fact, the current for PLL (Kpd) is reduced to minimize the spurs, too.

    Thanks in advance.

    BR,

    Pedro

  • 0 in reply to user277644
    TI__Guru** 108330 points
    Hi Pedro,

    For this kind of spurs, right, reducing the loop bandwidth is the most effective way of spurs reduction.
    Another thing you may try is to use 3rd order modulator. I think this setting should be better than 2nd order.
    you may also try to enable dither, phase noise may increase in return for a smaller spurs.
  • 0 in reply to Noel Fung
    Prodigy 120 points

    Hi Noel,

    Thank you for your feedback.

    Yes, I have already reduced slightly the loop bandwidth (increasing R4) and I have adjusted the PLL input level to meet the data sheet specification (Min. -15dBm) and with these two changes, the requirements of spurs attenuation are met.

    I had already checked order 3 for delta-sigma modulator, but the sub-fractional spurs are increased, and EVM of oscilator is slightly decreased.

    Related to dither,this could be another option but noise phase is increased and this parameter is critical for our application.

    The results reducing the loop bandwidth and adjusting the input level of PLL are OK.

    Thank you very much for your support.

    BR,

    Pedro