LMK04828: Making Dynamic Digital Delay work

Ok, that's encouraging.  In case it's helpful, here is a complete transcript of the LMK initialisation sequence from reset (all numbers in hex):

PLL[000] <= 80
PLL[100] <= 00
PLL[101] <= 55
PLL[103] <= 00
PLL[104] <= 00
PLL[105] <= 00
PLL[106] <= f9
PLL[107] <= 30
PLL[108] <= 00
PLL[109] <= 55
PLL[10b] <= 00
PLL[10c] <= 20
PLL[10d] <= 00
PLL[10e] <= f0
PLL[10f] <= 11
PLL[110] <= 05
PLL[111] <= 55
PLL[113] <= 07
PLL[114] <= 00
PLL[115] <= 00
PLL[116] <= 01
PLL[117] <= 01
PLL[118] <= 00
PLL[119] <= 55
PLL[11b] <= 00
PLL[11c] <= 00
PLL[11d] <= 00
PLL[11e] <= f9
PLL[11f] <= 01
PLL[120] <= 05
PLL[121] <= 55
PLL[123] <= 00
PLL[124] <= 00
PLL[125] <= 00
PLL[126] <= f1
PLL[127] <= 00
PLL[128] <= 05
PLL[129] <= 55
PLL[12b] <= 07
PLL[12c] <= 00
PLL[12d] <= 00
PLL[12e] <= 01
PLL[12f] <= 03
PLL[130] <= 05
PLL[131] <= 55
PLL[133] <= 00
PLL[134] <= 00
PLL[135] <= 00
PLL[136] <= f1
PLL[137] <= 30
PLL[138] <= 00
PLL[139] <= 00
PLL[13a] <= 0c
PLL[13b] <= 00
PLL[13c] <= 00
PLL[13d] <= 08
PLL[13e] <= 03
PLL[13f] <= 0b
PLL[140] <= 00
PLL[141] <= 00
PLL[142] <= 00
PLL[143] <= 91
PLL[144] <= 00
PLL[145] <= 7f
PLL[146] <= 10
PLL[147] <= 1b
PLL[148] <= 02
PLL[149] <= 42
PLL[14a] <= 02
PLL[14b] <= 16
PLL[14c] <= 00
PLL[14d] <= 00
PLL[14e] <= 00
PLL[14f] <= 7f
PLL[150] <= 43
PLL[151] <= 02
PLL[152] <= 00
PLL[153] <= 00
PLL[154] <= 78
PLL[155] <= 00
PLL[156] <= 0d
PLL[157] <= 00
PLL[158] <= 96
PLL[159] <= 00
PLL[15a] <= 0d
PLL[15b] <= df
PLL[15c] <= 20
PLL[15d] <= 00
PLL[15e] <= 00
PLL[15f] <= 0b
PLL[160] <= 00
PLL[161] <= 3d
PLL[162] <= 45
PLL[163] <= 00
PLL[164] <= 01
PLL[165] <= 7d
PLL[171] <= aa
PLL[172] <= 02
PLL[17c] <= 15
PLL[17d] <= 33
PLL[166] <= 00
PLL[167] <= 01
PLL[168] <= 7d
PLL[169] <= 59
PLL[16a] <= 20
PLL[16b] <= 00
PLL[16c] <= 00
PLL[16d] <= 00
PLL[16e] <= 13
PLL[173] <= 00
PLL[143] <= 11

>>> step_delay()
PLL[129] <= 33
PLL[12e] <= 01
PLL[139] <= 02
PLL[141] <= 20
PLL[143] <= 13
PLL[144] <= df
PLL[142] <= 01

At the >>> prompt above I check the alignment of DCLKout10 against CLKin on the oscilloscope, and then make the final seven assignments to try and step the phase.

Ok, so "24 hrs" was a bit optimistic ... but could I please have a response to this inquiry?  As you say, I seem to be following the documentation correctly, so I am at a loss.

Hi Michael

Sorry for the relay in response.

In the step 1 & 2, please also program 3 to DCLKout10_DDLYd_CNTH & DCLKout10_DDLYd_CNTL. You can find those registers in Dynamic Digital Delay section in the TICSpro as shown below:

After that you can continue the steps 3-8 and the dynamic digital delays should be working. Let me know if you see any issue,

Best regards

Puneet

“ If this answered your question, please click “This Resolved My Issue” button.

Alas, I have already tried this.    These registers are not documented in SNAS605AR, so at first I assumed they were specific to the LMK04828-EP, but I have tried adding them to the procedure with no effect.  Here is the transcript of my updated attempt to step:

>>> step_delay()
PLL[129] <= 33
PLL[12a] <= 33
PLL[12e] <= 01
PLL[139] <= 02
PLL[141] <= 20
PLL[143] <= 13
PLL[144] <= df
PLL[142] <= 01

As you can see, the only difference is the assignment you suggest.

This does seem to work.

So let me confirm.  The procedure seems to be:

1. For normal operation ensure CLKin_OVERRIDE = 0 and DCLKoutX_DDLY_PD = 0
2. All of DCLKoutX_DDLY_CNT{H,L} and DCLKoutX_DDLYd_CNT{H,L} should be set for a single delay step (as described in 9.3.3.2).
3. Ensure that DDLYdX_EN is set to 1
4. Write 1 to DDLYd_STEP_CNT

Some notes:

• I'm finding that the setting of DCLKoutX_DDLY_PD doesn't seem to make a difference!  Clearly I'll leave it set to 0 for safety.
• Of course, the disabling effect of CLKin_OVERRIDE is undocumented; I'd set this as I was nervous of automatic clock selection activating unexpectedly.
• As already remarked, DCLKoutX_DDLYd_CNT{H,L} are undocumented for the LMK04828.
• The LMK04828-EP documentation (SNAS703) makes a confusing remark on page 28 (section 9.3.3.2): "after a divider sync it is not permitted to change either of these values".  At what point does a "divider SYNC" occur?  I guess this may be a follow up question.
• The documentation (9.3.3.3) mandates setting SYSREF_MUX = 2 and SYNC_MODE = 3, but it's not clear to me that these play any role.  Indeed, delay stepping seems to occur ok with SYNC_EN = 0.

What is the status of the documentation for this device?  I listed the documentation I found at the start of this thread.  SNAS703 looks like an update to SNAS605AR, but specifically does not appear to cover the non -EP devices.  I'm not sure though, maybe the only substantive difference between the LMK04828 and the LMK04828-B is the documented oscillator ranges of the VCOs.

I seem to have two outstanding questions.  Do I need to raise these separately, or as part of this thread?

1. What is the true minimal Dynamic Digital Delay configuration?  In particular, what do I do with the SYNC infrastructure?
2. What do I need to do to be 100% confident that my clock outputs are synchronous after startup?  At present I'm not doing anything apart from setting and then resetting SYSREF_CLR, and I seem to be seeing synchronous outputs ... but is this just luck?