I'm using the LMK04828B eval board in the same configuration I plan to use on my design. That is fairly straightforward JESD204B clock distributor.
I have an external 10 MHz clock source in OSCin driving PLL2 and VCO0 = 2400 MHz. PLL2 is locked and I see the desired clocks on the DCLK outputs (100 MHz LVDS). However, I cannot see my desired 12.5 MHz on SYSREF / SDCLK outputs. I know the outputs of the IC work because I can set the SDCLK ouputs to "Device Clock" and I see the 100 MHz output. Reverting back to "SYSREF" just gives a DC output and no clock.
Everything looks setup correctly for a continuous 12.5 MHz and I've tried trial and error clicking boxes to no avail.
.tcs file saved if that helps.
