hello,
Our setup in short:
We are implementing a Xilinx FPGA-DAC JESD204B path:
- The implementation is a 9GHz/8bit single link/single DAC from DACLKSE input (DAC PLL is not used), over 8 lanes.
- LMK04828 distributes the clock tree to FPGA (SYSREF, DEVCLK, serdes clock) and DAC (SYSREF).
DAC’s CLKTXP/N supplies a 3GHz signal via external dividers to the LMK (LMK input is 93.75MHz). - Xilinx FPGA implements the JESD204B core and PHY.
- LMFSHd = 81180
The issue:
Our setup worked fine.
After inputting some changes in the LMK04828 configuration (removing unnecessary operations), the DAC started responding continuously with SYNC assertions.
This happened as soon as the JESD core started sending the K28.5 symbols.
This was accompanied by DAC JESD_ALM_Ln stating 8/10 errors, code sync errors and FIFO errors.
We checked electrically all LMK clocks signals, eye opening on DAC Rx, symbols sent from the JESD core. All seemed fine.
After starting to bring back changes input to the LMK (which seemed unnecessary at the time, thus removed), one change was the solution.
We toggled CLR_PLL2_LD_LOST (H then L) to be able to correctly read RB_PLL2_LD_LOST.
We deleted this toggling we didn't see any correlation to LMK operation (it was used to debug the LMK).
Seems there is some effect.
Can you explain?
Thank you
Gil
