LMX2594: phase changing

Feiran LIu

Part Number: LMX2594

Hi,

I have a question about phase change. We want to sweep the phase in very short time. I noticed that every time we change the phase, we need program register 0 to calibrate it. Can we get rid of the calibration? Can this chip finish changing phase in several ns? What is the fastest time to change the phase?

Thanks

over 7 years ago

0 Simon Damphousse over 7 years ago

TI__Expert 5370 points

Dear Feiran,

thank you for reaching out. Let me answer this shortly.

Regards, Simon.

0 Simon Damphousse over 7 years ago in reply to Simon Damphousse

TI__Expert 5370 points

Dear Feiran,

the assumption i make is that you are locked on a specific frequency and you are trying to change the phase of the signal with respect to the reference.

You can change the phase if you place the device in frac mode (MASH_RESET_N=1). You then enable mash seed (MASH_SEES_EN=1) and send a one time value in the DS using the mash seed entry (MASH_SEED). This number with each write will add for one clock cycle in the DS engine changing the phase of the DS and hence the phase of the signal. Each time you add a number (perform a write), you change the phase on the fly.

You do not need to reset re calibrate the device in this case.

I hope this helps.

Regards, Simon.

0 Feiran LIu over 7 years ago in reply to Simon Damphousse

Prodigy 90 points

Hi Simon,

Thank you for your quick response. Now I can get rid of calibration for phase changing. But how long can settle the phase changing, for example, from 0 degree to 15 degree? From my measurement, it takes around 5 us. Can the phase be stable in several ns?

Best,
Feiran

0 Simon Damphousse over 7 years ago in reply to Feiran LIu

TI__Expert 5370 points

Dear Feiran,

The settling and change of phase will depends mainly on the dynamic of the loop. I do not have numbers but I would say usec range not nsec range for sure. It also depends of what is your criteria for settling....

Given let's say a 200 kHz loop bandwidth, I would guess settling to be around 20 us easy...

I hope this helps.

Regards, Simon.

0 Feiran LIu over 7 years ago in reply to Simon Damphousse

Prodigy 90 points

Did you mean when I write MASH_SEED to PLL register, the PLL will start to shift the phase after one OSC clock cycle. Then the phase will be stable after around 20 us? So the total time for changing the phase is about (20 us + OSC clock cycle)?

0 Simon Damphousse over 7 years ago in reply to Feiran LIu

TI__Expert 5370 points

Feiran,

here is what will happen. As soon as you send the mash seed, the delta sigma calculator operating on will now have a different state which will create a different phase relationship for the PLL and now the loop will have to dynamically lock onto this new phase. The loop speed is governed by the loop BW of your PLL.

for example, a 200 kHz LBW could take as much as 4/200e3 (20 usec) in sec

I hope this helps.

Regards, Simon.

0 Feiran LIu over 7 years ago in reply to Simon Damphousse

Prodigy 90 points

Is there any PLL with phase synchronization can lock phase shift in nsec? Does TI has this kind of product?

0 Simon Damphousse over 7 years ago in reply to Feiran LIu

TI__Expert 5370 points

Feiran,

changing phase in nsec time frame is not very practical with a PLL. A very hgh speed DAC could do that and TI has these.

I hope this helps,

Regards, Simon.

0 Feiran LIu over 7 years ago in reply to Simon Damphousse

Prodigy 90 points

Thank you. That make sense.

0 Simon Damphousse over 7 years ago in reply to Feiran LIu

TI__Expert 5370 points

You are welcome. TI has DAC up to 9 GHz if not mistaken. please check their offering. regards, Simon.

Clock & timing

Clock & timing forum

LMX2594: phase changing