CDCM6208: one question about CDCM6208 's application

Oliver Ou

Intellectual 2845 points

Part Number: CDCM6208

Hi,

Customer wants know if CDCM6208 can support below PCI-E application.

Can you help to give some comments?

Input : PRI: PCI-E clock 100Mhz HCSL

SEC:backup clock 100Mhz LVPECL

Output: Y0: PCI-E clock 100Mhz

Y1: PCI-E clock 100Mhz

Y2: PCI-E clock 100Mhz

Y3: PCI-E clock 100Mhz

Y6&Y7: 125Mhz for FPGA

Thanks.

over 7 years ago

0 Simon Damphousse over 7 years ago

TI__Expert 5370 points

Dear Oliver,

I encouraged you to download the CDCM6208 software which include a frequency planner that is very well done.

The frequency plan you are proposing is fine with this device. You generate 2500 MHz from 100 MHz and then divide by 20 and 25...

I hope this helps,

Regards, Simon.

0 Oliver Ou over 7 years ago in reply to Simon Damphousse

TI__Intellectual 2845 points

Hi Simon,
Can we use DCDC for power input or need high performance LDO to achieve <1ps Jitter at 100MHz application?

Thanks.

0 Patrick Kammermayer over 7 years ago in reply to Oliver Ou

TI__Expert 5325 points

Hello Oliver,
this part was characterized using lab supplies and external LDOs. As CDCM6208 has LDOs internally there is a good noise rejection, still when you intend to use a switcher to supply it, you will have to take care to design the supply decoupling carefully, so that the deterministic noise is not transfered to the clocks. You can expect about 350 fs from a clean supply for V1 PinMode 2 with 100 MHz HCSL output.

Best regards,
Patrick

0 Oliver Ou over 7 years ago in reply to Patrick Kammermayer

TI__Intellectual 2845 points

Hi Partick,
The end customer still wants to confirm if CDCM6208 is PCIE clock compliant. Can you give some comments for this?

Thanks.

0 Patrick Kammermayer over 7 years ago in reply to Oliver Ou

TI__Expert 5325 points

Hello Oliver,
please let me know the DCDC switcher part number. I will have to make a typical measurement to see what the general performance impact is.

Best regards,
Patrick

0 Oliver Ou over 7 years ago in reply to Patrick Kammermayer

TI__Intellectual 2845 points

Hi Patrick,
We have asked customer to used a LDO to provide bias power. At this condition, if CDCM6208 is compatible with below PCIE application?
Dose PCIE have any special requirement for clock performance? I don't familiar the standard.

-----
Input : PRI: PCI-E clock 100Mhz HCSL

SEC:backup clock 100Mhz LVPECL

Output: Y0: PCI-E clock 100Mhz

Y1: PCI-E clock 100Mhz

Y2: PCI-E clock 100Mhz

Y3: PCI-E clock 100Mhz

Y6&Y7: 125Mhz for FPGA

Thanks.

0 Patrick Kammermayer over 7 years ago in reply to Oliver Ou

TI__Expert 5325 points

Hello Oliver,

yes, there are detailed specifications for PCIe clocks. There are multiple configurations possible and to be tested. For a quick overview, check out this blog by Julian.

Best regards,

Patrick

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CDCM6208: one question about CDCM6208 's application