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LMK03328: Output frequency support

Part Number: LMK03328

Hi,

Confused with the TICS Pro software for calculating the required PLL.

Below is my requirement. Can anyone please help me with this implementation ASAP.

The input is 25MHz on SECREF. And PRIREF is not present.

Thanks & Regards,

Nanjunda M 

  • Hi Nanjunda,

    I reviewed your schematic. Unfortunately you cannot use one LMK03328 to generate all of four of the frequencies.

    Here is some schematic feedback for using LMK03328 to generate the 125MHz, 135MHz, and 150MHz rails:

    • Replace C2507, C2508, C2509 with 10uF capacitors
    • Rearrange outputs for best performance:
      • VCO1 = 5250 MHz
      • VCO2 = 5400 MHz
      • OUT0 = 135 MHz
      • OUT1 = 135 MHz
      • OUT2 = 135 MHz
      • OUT3 = 135 MHz
      • OUT4 = disabled
      • OUT5 = disabled
      • OUT6 = 150 MHz
      • OUT7 = 125 MHz
    • I recommend the following loop filter capacitor values
      • CG_LF1 = 3.3nF

      • CG_LF2 = 3.3nF

    Kind regards,
    Lane

  • Hi Lane,

    Why can't we generate the 2 - 148.5MHz clocks?

    Can't we use input SECREF to generate the Out6 and 7 and VCO2 to generate the 2 148.5MHz?

    Please let me know.

    If you have any solution that can involve PRIREF is also fine for me. I have an option to implement that too.

    Please let me know ASAP.

    Thanks & Regards,

    Nanjunda M

  • Hi Nanjunda,

    You need another PLL to generate the 148.5MHz clock based on the output frequencies needed and the VCO range of this device. The 148.5MHz it cannot be divided from the same VCO as the 135MHz clock or 125MHz and 150MHz clocks.

    One option is to supply a 148.5MHz signal to PRIREF, and output PRIREF on OUT4/OUT5 (PLL bypass). This works well with the frequency plan from my previous post.

    Kind regards,
    Lane
  • Hi Lane,

    In the tool I saw a option to use the SECREF (25MHz) to generate the clock for 125M and 150MHz. Whether this is possible?


    Thanks & Regards,
    Nanjunda M
  • Hi Nanjunda,

    Yes, use the 25MHz XTAL on SECREF. It is also used to synthesize the 135MHz.

    Kind regards,
    Lane
  • Hi Lane,

    Changed a bit of the schematics.

    Please find the below.

    Output0: 148.5MHz

    Output1: 148.5MHz

    Output2: 125MHz

    Output3: 125MHz

    Output4: 135MHz

    Output5: 135MHz

    Output6: 150MHz

    Output7: 135MHz

    Could you please help me with, options for input REFCLK's i.e. PRIREF & SECREF.

    Thanks & Regards,

    Nanjunda M

  • Hi Nanjunda,

    Before there were four copies of 135MHz and one copy of 125MHz. Now there are three copies of 135MHz and two copies of 125MHz. Which is correct?

    Assuming your most recent post is right, I recommend to switch OUT6 and OUT7 so that the 135MHz outputs are adjacent. You can use 135MHz on PRIREF and bypass to OUT4 / OUT5 / OUT6. You can use this 135MHz reference to generate the 125MHz, 148.5MHz, and 150MHz as well.


    (this image doesn't show the 135MHz bypass on OUT4/5/6)

    The option in the image above was found using the WEBENCH Clock Architect Tool. Use this tool to find different clocking solutions for your application:

    Kind regards,
    Lane

  • Hi Lane, 

    I'm looking for all LVDS outputs.

    Could you please help with LVDS outputs(all), instead of LVCOMS.

    Thanks & Regards,

    Nanjunda M

  • Nanjunda,

    LMK03328 has programmable output drivers. If you are using the LMK03328EVM and TICS Pro, you can select the output format as LVDS in the Outputs Tab of TICS Pro.

    Kind regards,
    Lane
  • Hi Lane,

    The question was, whether the LMK03328 support my requirements with LVDS outputs requirement?
    I tried to get one from the Webench, but I could not get a solution with LVDS outputs with my requirements.

    Please let me know if you can get the things right there.

    Thanks & Regards,
    Nanjunda M
  • Hi Nanjunda,

    Yes, the LMK03328 can support your requirements using LVDS outputs.  Let me know if you have additional requirements to consider.

    You can use the same frequency plan I generated in WEBENCH from the previous post. Note: the block diagram does not show the 135MHz bypass outputs on OUT4/5/6

    Kind regards,
    Lane