Glitch free clock disable

user4946482

Other Parts Discussed in Thread: LMK00804B, LMK00725

We need to disable the output of a MAX3761 in an application which is sensitive to glitches. The disable of the MAX3761 isn't fast enough and produce glitches on the output. I'm interested in a clock buffer which supports glitch free clock interruption/disabling with a speed rate up to 500 MHz. Do you have any recommendation? We can't use any PLL solution as our clock changes non stop.

over 7 years ago

0 Alan O over 7 years ago

TI__Mastermind 32575 points

The following clock fanout buffers have synchronous clock enable functionality for glitch-free clock enable/disabling. Both devices have very low additive jitter as well.

For differential/LVCMOS input to LVCMOS output up to 350 MHz, you can consider LMK00804B.

For differential/LVCMOS input to LVPECL output up to 650 MHz, you can consider LMK00725.

Alan

0 user4946482 over 7 years ago in reply to Alan O

Prodigy 40 points

Thanks Alan.

I've just searched up to 4 output ports :-)

Clock & timing

Clock & timing forum

Glitch free clock disable