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LMX2571: FPD minimum value

Mateusz Drewniak
Prodigy 80 points

Part Number: LMX2571
Other Parts Discussed in Thread: CODELOADER,

Hi

I have a question about minimum frequency on the Phase Detector. Is there any minimum frequency limit for the phase detector? I have a problem with R Counter set. When I use R Counter = 12, everything is ok and I see Fout on spectrum analyzer. But when I set R Counter to 13 and up, PLL is not work.  I send my screenshots with my configuration in CodeLoader. Maybe I cross other parametr?


Regards
Mateusz

  • 0
    TI__Mastermind 28031 points

    Mateusz,

    I encourage you to use the TICSPro software;  it is an upgraded version of CodeLoader.

    Looking at your programmable settings, I do not see anything wrong. 

    I am thinking that perhaps this has something to do with the loop bandwidth getting very narrow and unoptimized as a result of the lower phase detector frequency.  If the phase detector frequency or charge pump gain is changed drastically from what the loop filter was originally designed for, then it will not be very well optimized.

    To test this theory, try increasing the charge pump current and see if this fixes the issue.  If so, the reason would be is that the higher charge pump current corrects for the lower phase detector frequency.

    Regards,

    Dean

  • 0 in reply to Dean Banerjee
    Prodigy 80 points
    Hi Dean, thanks for your fast answer. At the beginning We also had theory like You, and checked it first. I made more experiments with LMX2571 evaluation board and can write you new fact. When I turn off calibration (FCAL_EN) LMX2571 works OK and allow to decrese FPD (lat the same VCO frequency). This suggest that the problem is in VCO calibration sequency. I know that calibration time depends FPD but I did a lot of test and LMX2571 still does't works with calibration on.
    Sorry for this curiosity of details but we plan use this IC to serial production and We have to know does IC behave as provided for in the documentation
    Regards,
    Mateusz
  • 0 in reply to Mateusz Drewniak
    TI__Mastermind 28031 points
    Mateusz,
    It sounds like if you calibrate with a higher phase detector frequency with FCAL_EN=1, then it works fine.

    But if you calibrate with a low phase detector frequency with FCAL_EN=1, then there are locking problems.

    However, if you lock with a high phase detector with FCAL_EN=1, then set FCAL_EN=0 and then lower the phase detector frequency, it retains lock.

    Assuming this, it sounds like an issue with the VCO calibration. The VCO has many small frequency bands, and if the calibration chooses the wrong one, then you are stuck there.

    The phase detector frequency impacts the state machine clock for calibration. Maybe it is getting too slow. Try this:
    Set your R divider to 16 to get a phase detector frequency of 1.25 MHz.
    Set FCAL_SHIFT_RIGHT (R0[3:2]) = 2 . This will increase the state machine clock by a factor of 4. Also you can keep this word set to 2 and increase the R divider to 32 and see if this works.

    From a performance point of view, lowering the phase detector frequency to these lower frequencies will hurt VCO calibration times, PLL phase noise, and likely spurs as well.

    Regards,
    Dean