LMK03328: Clock input timing

Dice-K

Mastermind 7470 points

Part Number: LMK03328

Hello.
This quesition is about input timing of clock signal of PRIREF_P, PRIREF_N, SECREF_P, SECREF_N.

Is there no problem if the clock input is fixed before the input of the PDN pin changes from Low to High?

Are there other timing and time regulations?

If the PDN pin is Low, I think that there is no problem because LMK03328 is disabled.

Regards,
Dice-K

over 7 years ago

0 Shawn Han over 7 years ago

TI__Genius 9920 points

Hi Dice-K,

If LMK03328 would be reprogrammed by I2C, it is no problem for no reference clock ready before PDN low to high transition.

If LMK03328 used hard pin mode or EERPOM mode, then PDN low to high would make LMK03328 release reset, and load default settings, the important actions is auto-calibration for internal VCO, which need a valid reference clock. So LMK03328 datasheet descripts a section about "12.4.7 Slow Reference Input Clock Startup". A delayed PDN rising edge is needed.

Regards,
Shawn

Clock & timing

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LMK03328: Clock input timing