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CDCE813-Q1: CDCD813-Q1 Default Configuration

Part Number: CDCE813-Q1
Other Parts Discussed in Thread: CDCE913

Hi,

Noticed there was a new release of the CDCE813-Q1 datasheet a couple of days ago.

The default configuration now has all outputs at tristate and the S0 pin does nothing..  (Was wondering what was going on with me board..)

So the default config for Reg 02: Y1_ST0 is now 01b same as the Y1_ST1 setting..

Is the 813 device a valid one to use?

Seems like it was made for a specific purpose as a slight change on the default configuration of the 913? Which was good for us as we wanted a simple jitter remover like Figure 13..

Now have to implement full configuration via i2c. Luckily looks like the 913 kernel clk driver will function with the 813 given a couple of tweaks to settings..

Is there any reason to use the 813 vs the 913 now that the default is broken? ie which one are customers using the most is what I'm getting at..

Cheers

  Richard

  • Also I've noted that the datasheet specifies Fvco (pll Output frequency) to have a min of 70MHz on the 813 part in the Electrical Characteristics table.
    Yet the chart (Figure 1) shows power usage of pll all the way down to and Fvco of 10Mhz.
    Is the 70Mhz min in the table simply to guarantee the jitter figure? Or is it more a fundamental range of the pll's VCO?
  • Hello Richard,
    CDCE813 and CDCE913 are same parts. Only difference is in the default configuration. You can use either of the devices with no performance difference.
    Best regards
    Puneet
  • Hi Richard,
    The VCO might work down to 10MHz, but it is not guaranteed by datasheet and we are not testing this in production. I will not recommend to use this part for the VCO range outside the datasheet limits specified in electrical table.
    Best regards'
    Puneet