LMX2581: Phase Noise Optimization

LBDube,

1. Assume that any signal generator frequency has absolutely horrible phase noise, as this is almost always the case. A signal generator costing a lot of money or claiming to be low nose does not make it low noise.

One useful experiment to do is to change the frequency. For instance, if this is signal generator noise, then keep the phase detector frequency a constant 10 MHz and try this: Try 10 MHz input with R=1 for Fpd=10 MHz, then try 20 MHz with input R=2 for Fpd=10 MHz, then try 100 MHz with input R=10 for Fpd=10 MHz, then try 1000 MHz input with Fpd=100 for Fpd=10 MHz. They all should have the same phase noise, but if the higher input frequency has better phase noise, typically this points to a noisy signal generator.

2. Assuming a noiseless input reference, you should expect a lower loop bandwidth as it is a function of the phase detector frequency , charge pump gain, and VCO gain. In your case, the charge pump gain is pretty close, but the phase detector frequency is half, which should reduce the loop bandwith. According to our PLLatinum Sim tool, the original loop bandwidth is 21.7 kHz (But this depends on the VCO core selected, which could be VCO2 or VCO3 for 2.7 GHz). Now if you change your parameters from the defaults to the ones for your setup (Kpd = 3.0 vs. 2.4, Fpd = 10 vs 20, Fvco = 2200 vs 2700), this reduces the loop bandwidth from 21.7 to 13.6 (if device chooses VCO2) or 17.4 kHz (if device chooses VCO1). Actually the 13.6 kHz looks close to what you are getting. The "peaking" likely has nothing to do with phase margin, but rather the VCO noise cropping inside the loop bandwidth and causing this effect. The default is for the device to start at VCO3, which means it will try VCO2 if it works, so likely you are looking at VCO2.


So in summary:
1. Ensure that you are not looking at the input reference noise.
2. Ensure that his is not due to loop dynamics. i.e. Set the VCO to VCO1 vs. VCO2 and see if there is a difference. Try an apples to apples comparison with EVM instructions and change Fvco=2700 and Fpd=20 MHz.
3. Upgrade to TICSPro (www.ti.com/.../TICSPro-SW) as it is easier to use. Unless you are using a parallel port cable and not the parallel port to program USB2ANY, there is no incentive to use CodeLoader. The upgrade is painless and the form and feel are very similar to Codeloader.
4. Try our PLLatinum Sim tool (ti.com/tool/PLLatinumSim-SW). It models the impact of changing the phase detector frequency, VCO core, loop filter, and charge pump gain. Also, if I put in your 10 MHz phase detector frequency with VCO2 as the core, it also predicts the peaking in the phase noise right at 10 kHz.

Regards,
Dean

Hi LB,

I suggest you contact your local sales representative to get a USB2ANY.
For the reference signal, we have seen many failure cases using the 10MHz or 20MHz output from a signal generator. You can compare the result with the 10MHz output from the signal generator and with the 10MHz reference output from the rear panel of the signal generator. You should see the difference.
As for the vibration, if you are using a crystal-based reference clock to a PLL, then it is the instability of the reference clock that makes the PLL not stable or unlock. The PLL can be make to react to the change faster by making the lock time faster. That means you need a little bit wider loop bandwidth; around 50 degrees phase margin. Use PLL Sim to find out a balanced solution.