Part Number: CDCM6208
Hi,
I would like to use the CDCM6208 to generate clocks locked to PCIe/MGT clock arriving from a daughter board for the MGT receivers onboard artix 7. I would like to know if the LVDS clocks can be directly connected to the clock inputs or is some sort of biasing like given in the EVM schematics is required ? Also, is there a default input mode ? can this be selected through I2C/SPI connection ?
Thank you !
Mugundhan
Hi Mugundhan，
A LVDS signal could be connected to CDCM6208 REF directly, refer to below figure DC connection.
The LVDS signal also could be connected with AC coupling mode.
The REF input type could be selected in register 4 through SPI / I2C.
In pin mode, there are default types on PRI_REF and SEC_REF (LVDS, LVCMOS,XTAl), depends on which pin mode is selected.
Regards,
Shawn
Hi Mugundhan,
For PCIe REFCLK to CDCM6208 REF, it is recommended to use AC mode, as Figure 19.
Circuits in the Left of AC caps depends on PCIe REFCLK driver. Normally, it is HCSL type. Then the driver need the DC path 50 Ohm to GND for each line.
The HCSL common mode voltage can't reach CDCM6208 differential REF spec VICM (0.8~1.5)V. But 700mV swing is fine.
That's why we need AC coupled and rebuild new bias for CDCM6208 input.
Please double check PCIe REFCLK spec.
If PCIe REFCLK driver bias or Voltage_output_common_mode could be in below spec. then DC coupled also is possible.
If you use the CDCM6208 in pin mode it is possible to pulldown the output power supplies for unused outputs Yx to save power. In this case there is no need to terminate the output pins.
If you use CDCM6208 with programming interface like SPI or I2C, you can simply disable the unused output stages to minimize the power consumption.
Leave unused outputs unconnected and pull-down the relevant output supply pin. 2-3kohm pulldown to GND should be OK.
Regards,
Shawn
