LMK04610: LMK04610

yeshayahou Baracassa

Part Number: LMK04610
Other Parts Discussed in Thread: CDCLVP1102, , CDCLVC1102

Hi !

I design to connect a difference clock of 410Mhz to differential clock input pins OSCinp/n ,using only PLL2 .The clock is a sinus wave converted to differential wave by a transformer with 100 ohm termination, then AC couple .

Each input pin have a 1.3Vptp signal amplitude.

Should i have to protect the input pins from over amplitude voltage when device is un-power and the clock is active?

The datasheet require a maximum voltage of -0.3V to (VDD_IO+0.3) ,which give +-0.3V when un-power.

If the answer is positive then can you advise how to implement it?

Thanks

Yeshayahou

over 7 years ago

0 Lane Boyd over 7 years ago

TI__Genius 16845 points

Hi Yeshayahou,

Yes, the voltage on the clock input pins cannot exceed VDD_IO + 0.3V; you need to disable the reference clock source when the device is powered off.

One way to do this is by disabling the reference clock.
Another method is to insert a clock buffer between the source and LMK04610. You could use a single-ended clock buffer such as CDCLVC1102, or the differential clock buffer CDCLVP1102. Both buffers have an output enable pin, and it can be used to disable the input to the LMK04610.

Kind regards,
Lane Boyd

0 yeshayahou Baracassa over 7 years ago in reply to Lane Boyd

Prodigy 200 points

Thanks
yeshayahou

Clock & timing

Clock & timing forum

LMK04610: LMK04610