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CDCM6208: In case of LVCMOS input(Single ended input)

Hirotaka Matsumoto
Guru 27585 points
Part Number: CDCM6208


Hi all

Would you mind if we ask CDCM6208?

<Question1>
On the datasheet "Figure 15. LVCMOS Input DC Configuration During Device Test", we would like to confirm "Offset = VDD_PRI/SEC/2".
In case of DC coupling, it seems that there is no requirement bias voltage.
What does "Offset = VDD_PRI/SEC/2" mean?

<Question2>
In case of Single-ended input, how does PRI_ or SEC_ REFN pin treat?
-Disable and 10kohm pull down?
-Disable and Open?

Kind regards,

Hirotaka Matsumoto

  • 0
    TI__Mastermind 32575 points

    1. "Offset" is referring to the mid-point of the single-ended input voltage swing (DC coupled) from the Signal Generator.  For a LVCMOS clock, there is no need to specify an offset voltage, since the LVCMOS driver's Voh/Vol levels will determine the relevant levels (Vih/Vil) at the xxxREF_P input.  Just make sure the VDD_xxx_REF voltage is powered accordingly for the LVCMOS input signaling levels (for example, VDD_xxx_REF should be powered 1.8 V for a 1.8-V LVCMOS input to xxxREF_P).

    2. When xxxREF_P is configured as LVCMOS input, the xxxREF_N should be pulled down with Rpd <=4.7 kohm.

    Regards,
    Alan