Other Parts Discussed in Thread: LMK05028, LMK05318
I have some questions about using the dynamic digital delay on the LMK04828. I have a 1 PPS signal coming into my FPGA, and I want to align the clock edge of DCLKout0 so that the clock comes right after when the PPS is detected by the FPGA.
I figure I can set up a counter in the FPGA that increments every clock cycle, and at every PPS detected: 1) outputs the value to a read-only register and 2) resets. Every PPS, I want to insert a DDLY of one VCO cycle and read the register. My theory is that by pushing the clock edge back incrementally, I should see a PPS cycle where the clock period in which the PPS is detected will 'jump' a cycle, which should result in the counter value being less by 1. If my logic is wrong, feel free to let me know, but I mostly just wanted to give a little context to my logic. The clock in question is 125 MHz
The sequence, as I understood it from the datasheet:
Set DCLKout0_DDLY_CNTH = C
Set DCLKout0_DDLY_CNTL = D
Set CLKout0_DDLY_PD = 0
Set DDLYd0_EN = 1;
Set SYNC_DIS0 = 0
Set SYNC_MODE (Reg 143) to SPI write (0x13)
Set SYSREF_MUX (Reg 139) to Pulser (0x02)
After that, am I understanding correctly that every time I write to DDLYd_STEP_CNT, the CNTH/CNTL are inserted for the number of clock cycles written to DDLYd_STEP_CNT?
Thanks
