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LMK04828: SYSREF setup issue

Mark Guastaferro
Genius 11645 points
Part Number: LMK04828
Other Parts Discussed in Thread: ADS42JB69, , ADS42JB69EVM

Need some help sorting out an issue with setting up SYSREF and the initial synchronization of SYSREF path.  Hardware configuration is using the ADS42JB69 EVM (which has the LMK04828 as the clocking device) conencted to an FPGA board (not a TI test board).

Goal is to set-up SYSREF to be in pulser mode using SPI programming (register 0x13E trigger).  Trying to basically follow the steps of section 9.3.2.1.1 in the data sheet. However, a SYSREF pulse comes out of the active SDCLKout output during this initialization process.  Is this expected?  We had the impression that setting SYSREF_CLR = 1 would prevent any SYSREF outputs during these steps. 

Also, we are trying to use the SPI Pulser mode to trigger this initial synchronization.  The steps in the data sheet use the SYNC pin and use SPI to toggle the pin polarity.  Does this matter? 

Attached is a text file of the LMK commands to set this up.  Any advice is appreciated. 

Fullscreen ads42jb69evm_FPGA..txt Download 
create ads42jb69evm.4th

s" /dev/spidev1.1" r/w open-file drop constant lmk
s" /dev/spidev1.2" r/w open-file drop constant adc

: config-lmk
  \ initial reg setting for LMK04828 so that
  \ source clock from J21 -> Clkin1 -> (bypassing PLL1 & PLL2) clock distribution path
  \   all divider/delay are bypassed except SYSREF DIVIDER, which must be active in order to generate SYSREF on SDCLK1/SDCLK3
  \   mimimual divisor value is 8
  \ DCLK2/SDCLK3 for on-board ADC
  \ DCLK8/SDCLK1 for ZC706 through FMC
  0x80 0x000 lmk lmkspi!
  0x10 0x000 lmk lmkspi!
  0x00 0x002 lmk lmkspi!
  0x00 0x100 lmk lmkspi!
  0x00 0x101 lmk lmkspi!
  0x02 0x103 lmk lmkspi!
  0x20 0x104 lmk lmkspi!
  0x00 0x105 lmk lmkspi!
  0xF0 0x106 lmk lmkspi!
  0x11 0x107 lmk lmkspi!
  0x00 0x108 lmk lmkspi!
  0x00 0x109 lmk lmkspi!
  0x02 0x10B lmk lmkspi!
  0x20 0x10C lmk lmkspi!
  0x00 0x10D lmk lmkspi!
  0xF0 0x10E lmk lmkspi!
  0x11 0x10F lmk lmkspi!
  0x00 0x110 lmk lmkspi!
  0x00 0x111 lmk lmkspi!
  0x02 0x113 lmk lmkspi!
  0x20 0x114 lmk lmkspi!
  0x00 0x115 lmk lmkspi!
  0xF9 0x116 lmk lmkspi!
  0x00 0x117 lmk lmkspi!
  0x00 0x118 lmk lmkspi!
  0x00 0x119 lmk lmkspi!
  0x02 0x11B lmk lmkspi!
  0x20 0x11C lmk lmkspi!
  0x00 0x11D lmk lmkspi!
  0xF9 0x11E lmk lmkspi!
  0x00 0x11F lmk lmkspi!
  0x10 0x120 lmk lmkspi!
  0x55 0x121 lmk lmkspi!
  0x02 0x123 lmk lmkspi!
  0x00 0x124 lmk lmkspi!
  0x00 0x125 lmk lmkspi!
  0xF1 0x126 lmk lmkspi!
  0x01 0x127 lmk lmkspi!
  0x00 0x128 lmk lmkspi!
  0x00 0x129 lmk lmkspi!
  0x02 0x12B lmk lmkspi!
  0x20 0x12C lmk lmkspi!
  0x00 0x12D lmk lmkspi!
  0xF9 0x12E lmk lmkspi!
  0x00 0x12F lmk lmkspi!
  0x00 0x130 lmk lmkspi!
  0x00 0x131 lmk lmkspi!
  0x02 0x133 lmk lmkspi!
  0x20 0x134 lmk lmkspi!
  0x00 0x135 lmk lmkspi!
  0xF9 0x136 lmk lmkspi!
  0x00 0x137 lmk lmkspi!
  0x44 0x138 lmk lmkspi!
  0x02 0x139 lmk lmkspi!
  0x00 0x13A lmk lmkspi!
  0x08 0x13B lmk lmkspi!
  0x00 0x13C lmk lmkspi!
  0x08 0x13D lmk lmkspi!
  0x00 0x13E lmk lmkspi!
  0x00 0x13F lmk lmkspi!
  0xF0 0x140 lmk lmkspi!
  0x00 0x141 lmk lmkspi!
  0x00 0x142 lmk lmkspi!
  0x93 0x143 lmk lmkspi!
  0x00 0x144 lmk lmkspi!
  0x7F 0x145 lmk lmkspi!
  0x07 0x146 lmk lmkspi!
  0x13 0x147 lmk lmkspi!
  0x03 0x148 lmk lmkspi!
  0x03 0x149 lmk lmkspi!
  0x33 0x14A lmk lmkspi!
  0x00 0x14B lmk lmkspi!
  0x00 0x14C lmk lmkspi!
  0x00 0x14D lmk lmkspi!
  0x00 0x14E lmk lmkspi!
  0x7F 0x14F lmk lmkspi!
  0x42 0x150 lmk lmkspi!
  0x00 0x151 lmk lmkspi!
  0x00 0x152 lmk lmkspi!
  0x00 0x153 lmk lmkspi!
  0x78 0x154 lmk lmkspi!
  0x00 0x155 lmk lmkspi!
  0x0A 0x156 lmk lmkspi!
  0x00 0x157 lmk lmkspi!
  0x96 0x158 lmk lmkspi!
  0x00 0x159 lmk lmkspi!
  0x64 0x15A lmk lmkspi!
  0xF4 0x15B lmk lmkspi!
  0x20 0x15C lmk lmkspi!
  0x00 0x15D lmk lmkspi!
  0x00 0x15E lmk lmkspi!
  0x03 0x15F lmk lmkspi!
  0x00 0x160 lmk lmkspi!
  0x05 0x161 lmk lmkspi!
  0x44 0x162 lmk lmkspi!
  0x00 0x163 lmk lmkspi!
  0x00 0x164 lmk lmkspi!
  0x40 0x165 lmk lmkspi!
  0xAA 0x171 lmk lmkspi!
  0x02 0x172 lmk lmkspi!
  0x15 0x17C lmk lmkspi!
  0x33 0x17D lmk lmkspi!
  0x04 0x166 lmk lmkspi!
  0x00 0x167 lmk lmkspi!
  0x40 0x168 lmk lmkspi!
  0x43 0x169 lmk lmkspi!
  0x20 0x16A lmk lmkspi!
  0x00 0x16B lmk lmkspi!
  0x00 0x16C lmk lmkspi!
  0x00 0x16D lmk lmkspi!
  0x03 0x16E lmk lmkspi!
  0x60 0x173 lmk lmkspi!
  \ SPI write to 0x13E to generate a sync event (with pulser) to sync all delay/dividers
  0x00 0x13E lmk lmkspi!
  \ pwrdn sysref_ddly; release sysref_clr (end sysref setup procedure and go to normal operation); prevent sync event from affecting DCLK*/SDCLK*;
  0xF2 0x140 lmk lmkspi!
  0x13 0x143 lmk lmkspi!
  0xFF 0x144 lmk lmkspi!
;

: trigger-sysref-lmk
  \ after the config is done
  \ each SPI write to 0x13E to generate a sysref pulse that is 4-clock wide (due to /8 on SYSREF DIVIDER)
  0x00 0x13E lmk lmkspi!
;

  • 0
    TI__Expert 5370 points
    Dear Mark,

    I assigned your request to the right person. Thank you for your patience, he will answer Monday as he is out of office Friday.

    Regards, Simon.
  • 0
    TI__Mastermind 28590 points

    Hello Mark,

    You have the SDCLKoutY_DDLY registers = 0x00 (Bypass), change this to > 0 and then the SYSREF_CLR = 1 will prevent SYSREF output.  For best timing of SYSREF to device clock, you want SDCLKoutY_DDLY > 0.

    You are not required to use the SYNC_POL invert, you appear to have it setup correctly for SPI to generate the pulses as you have SYNC_MODE = 0x03 (SYNC SPI, Pulser).

    73,
    Timothy

  • 0 in reply to Timothy T
    TI__Genius 11645 points

    Hi Timothy

    Thanks for the suggestion, but it didn't seem to correct my issue.  I noticed that a SYSREF pulse will come out when the SYSREF_CLR bit is cleared back to 0 after sending the synch command via SPI.  Its as if the command is stored waiting for the SYSREF_CLR bit to be cleared.  This doesn't happen if I use the SYNC pin and SYN_POL to trigger the sync event. 

  • 0 in reply to Mark Guastaferro
    TI__Mastermind 28031 points
    Mark,

    I'm not as familar with this device as Tim, but he is out today, so I'll try at this. If it doesn't help, he can clarify when he gets back.

    In section 9.3.2.1.2, it says to set SYSREF_CLR=1 to avoid any unwanted pulses during startup. In section 9.3.2.1.1, it says to hold it high until step 4.

    I note that SYSREF_CLR is in register 0x143, whichi is the same as the SYNC_POL, SYNC_EN, and some other SYNC related bits.. I do wonder if you were to program register 0x143 again with the same value if this would fix this issue.

    Regards,
    Dean
  • 0 in reply to Dean Banerjee
    TI__Genius 11645 points

    Hi Dean,

    Your suggestion did not change the result, we still saw the unwanted pulse.  At this point, the steps were modified to use the SYNC pin polarity to trigger the divider sync as is shown in the data sheet and the unwanted pulse does not happen. Everything is working fine with this method and so we can close this issue.