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LMK04610: LMK04610

Menachem Segal
Prodigy 30 points
Part Number: LMK04610


Hi,

I plan to use the LMK04610 in my new design. For the CPU in the design I need a running clock right after reset (before chip programming).

For that reason I decided to use the OSCout output that drives PLL1 only (PLL2 bypass mode, figure 53 in datasheet) right after reset and later on I plan to switch to dual PLL mode (with PLL2 figure 51 in datasheet).

My questions:

  1. What is the SSB (dBc/Hz) phase noise difference of OSCout (at 122.88MHz frequency out) between PLL1 only (PLL2 bypass mode) and dual PLL mode?
  2. While doing the switching between the above modes should I expect PLL out-of-lock of  or any other drift?

Regards,

Menachem

  • 0
    TI__Guru** 110810 points
    Hi Menachem,

    After Vcc power up, LMK04610 OSCout will have an output signal which is the copy of the VCXO. You don't need to program it to PLL1 only mode. At this time, PLL1 and PLL2 are not working and the VCXO is operating in free-running mode. The output phase noise at OSCout is very similar to the VCXO except that at far-end, the phase noise may be a bit higher because of the noise floor of the output buffer.
    When PLL1 is engaged (PLL1 mode or dual PLL mode), close-in phase noise will degrade (depends on PLL1 loop bandwidth and the phase noise of the input clock).
    Before programming, the VCXO is free-running. During programming, the VCXO will be moving until it is locked. Lock detect will indicate lock only when the lock criteria as programmed are met.