LMK03318: i2c error

Hi Yuma Kudo,

When I2C communication with our device fails, have you attempted to communicate with the device using a different slave address? In soft pin mode, the device slave address is 10100xx (the two LSBs are determined by the GPIO1 pin).

Also, there is a note on page 52 of the datasheet: "The PDN pin of LMK03318 should be high before any I2C communication on the bus. The first I2C transaction after power cycling LMK03318 should be ignored"

I am using this device in soft pin mode. but GPIO1 pin is tied to 3.3V. 3.3V is stable and I think that the possibility that the slave address will change is extremely low.

"The first I2C transaction after power cycling LMK03318 should be ignored"
What does the sentence above mean?
Is it necessary to send it with 1 dummy command after power on (PDN L-->H) ?
For example
PDN L --> H
MPU LMK03318
Write R0 return NACK 1st command (dummy)
Write R0 return ACK 2nd command
Write R1 return ACK 3rd command
......

But, in our experiment, the NACK is returned after the second command, and the state does not change until reset (PDN L -> H).

Hi Yuma,

Thank you for the clarification. Can you please provide the date code of the samples that you have? An earlier generation of the silicon potentially had this issue that you are describing.

The data code of samples that I have is
69U
A7C7 G3

I have another date code sample, so I will try on that sample.
74U
A8VJ G3

Is this phenomenon (I2C error) certainly solved by putting the reset (PDN L--> H) again?
(Is there something that will not be solved until the power is turned off like latch-up?)

The same phenomenon occurred in the sample below.
74U
A8VJ G3
Is this behavior correct?

From the two different date-codes you shared, we confirmed the samples you have correspond to an early silicon revision.

In this early silicon revision, there was indeed a very low probability risk of device startup failure when PDN pin transitions (low to high) after the VDD supply voltage has ramped. The PDN startup failure rate we observed is very similar to what you observed. The early silicon revision can be identified by reading the reset/default value of 0x01 from Register R3 (REVID).

This PDN startup issue was fixed in the current production silicon, which can be identified by reading the REVID default value of 0x02 from Reg R3. If you order new LMK03318 parts/samples, you should receive the current silicon that does not exhibit the PDN startup issue, so the PDN pin functionality is robust now. The current LMK03318 datasheet reflects the REVID reset value of 0x02 for the current silicon.

We are curious when and where/how you purchased the samples you have.

Can you please send an email to clock_support@list.ti.com and provide the following info so we can track-down how you received the early silicon?

1. Company name with contact info
2. When, where, how you purchased these early revision LMK03318 samples (REVID = 0x01)? Include distributor name/info if not purchased directly from TI.
3. How many boards/positions you have assembled with these LMK03318 samples?

Thank you,
Alan

I send an email to clock_support@list.ti.com.
About 300 pieces of LMK03318 is already used. (mounted on board)
We need software countermeasures.
Should I post a question by e-mail?