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LMX2594EVM: LMX2594EVM

porat yifrah
Prodigy 150 points

Part Number: LMX2594EVM
Other Parts Discussed in Thread: LMX2594

Hi,

I have a question regarding measurements in LMX2594EVM (i defined the loop filter as described as example in user guide, see attached) .

Environment:

Fout: 8.31G

Oscillator: 100M - build in  (I tested also with external oscillator ) 

Loop filter - user guide (as is i got with EVM ) (see attached)

Kpd (CP) - 3mA

 

Result:

According to PLLSimulation i need to get spur in 10M @ -66.99 dBc but in my measurement i got the spur at -77.49 dBc. see attached. (~10 db difference )

 

Please advise.

 

Thanks,

Porat.Y

LMX2594.pptx

  • 0
    TI__Mastermind 28031 points

    Porat,

    Spurs are very difficult to predict and are modeled by many different factors, not all of which are modeled by the simulation.  This is why other simulations don't even try to model spurs at all, but I think that it adds value as it gives insight and understanding to.   10 dB is not unseen for errors in spur modeling, but is more than is typical or desirable.  For a given hardware and software setup condition, typically spurs vary less than 10 dB from my experience.

    I have good data to support the model used for 15 mA charge pump gain, but none taken at 3 mA, so maybe the FpdXtalk spur gets better at lower charge pump gain.

    Below is the calculations used to predict the spur levels for the FpdXtalk Spur.  Note that in the formula, I account for Fpd (Phase Detector Frequency), but not Kpd (Charge pump Gain). 

    For some devices I have seen that lowering the charge pump gain improves the Fpd spur, others not.

    The model I used had Kpd=15 mA always and you use 3 mA.  Maybe this is the difference.  See the model used below:

    Regards,
    Dean

  • 0 in reply to Dean Banerjee
    Expert 1585 points
    Hello Dean

    Does the spur calculation take in account the loop BW? Does the spur suppose to be attenuated by the loop or the coupling occurs in the VCO so the spur level is not affected by the loop BW?

    Thanks
  • 0 in reply to Izik
    Expert 1585 points
    One more question about the simulator:

    When I look on the plot PLL phase noise decomposition, I can see that the floor on 100Hz is -90dBc/Hz. So I assumed that my oscillator needs to be better than -105dBc at 100Hz offset in order not to degrade in PLL phase noise at this point. However, when I load a txt file with the oscillator phase noise, and I specify -120dBc/Hz at 100Hz offset and I get phase noise degradtion to -80dBc/Hz at the main phase noise plot of the pll.

    Can you please explain?

    Thanks
  • 0 in reply to Izik
    TI__Mastermind 28031 points

    Izik,

    The oscillator phase noise is multiplied up by 20*log(Fout/Fosc)

    So if your output frequency was 1 GHz and your input phase noise was -90 dBc/Hz at 10 kHz offset for a 100 MHz input, then this would actually translate to -90 +20*log(1GHz/100MHz) = -70 dBc at the output, assuming it was inside the loop bandwidth.


    Regards,

    Dean