CDC3RL02: Min spec of CLDO in datasheet

Chris Taylor10

Prodigy 20 points

Part Number: CDC3RL02

I am using 2.2uF X5R 6V3 20% ceramic capacitor on VLDO (pin B1).

At low temperature ~0deg C the LDO oscillates at ~ 1.2MHz causing 1.2MHz spurs on the CLK output.

I am certain the capacitance value remains above the minimum required value of 1uF at this temperature.

Is there any requirement for min or max ESR on the CLDO capacitor?

Thank you

Chris

over 6 years ago

0 Alan O over 6 years ago

TI__Mastermind 32575 points

Yes, the minimum ESR required for the CLDO cap is 100 milliOhms to ensure LDO stability over PVT. This was confirmed by the chip designer.

Alan

0 Chris Taylor10 over 6 years ago in reply to Alan O

Prodigy 20 points

Hi Alan,

Thanks for your reply.

Is there a maximum limit for the ESR?

Chris

0 Alan O over 6 years ago in reply to Chris Taylor10

TI__Mastermind 32575 points

The ESR range for CLDO is 100 to 1000 milliohm (plus +/-20% tolerance). This could be achieved using controlled-ESR cap for CLDO, or by adding a discrete resistor in series with the CLDO cap.

Regards,
Alan

Clock & timing

Clock & timing forum

CDC3RL02: Min spec of CLDO in datasheet