LMX2592: LMX2592 Phase Determinance

Ken White

Part Number: LMX2592
Other Parts Discussed in Thread: LMX2594,

Dean,

Our application provides an input reference clock of 1200MHz and requires 2 output clocks of 600MHz, preferably edge locked to the rising edge of the reference. We initially tried the LMX2594, but because of the fractional relationship between the input and output clocks (600/1200 = 1/2), that placed us in Category 3. Consequently, we could phase lock and synthesize a 600MHz output, but the software SYNC adjustment for phase deterministic operation wasn't available and our hardware control of the SYNC line is not sufficiently precise to achieve edge lock. Also, fine phase adjustment using the MASH_SEED technique is not available in Category 3.

Next, we tried the LMX2592 with VCO at 4800, output divisor at 8 and input divisor at 24. We were able to synthesize the 600MHz outputs AND utilize the MASH_SEED to perform extremely fine phase adjustments. However, the initial phase relationship between input and output clocks after power-up and register configuration is not deterministic. It seems to randomly select one of eight different phase relationships for initial lock. Any one of which would be fine since phase adjustment works very well. For our application, it seems that what we need is a hybrid of the LMX2592 and LMX2594.

Given our design requirements and PLL setup, is there any mechanism we can employ such as order of register programming, combinations of VCO or PFD settings, etc. to achieve a consistent initial phase relationship? If so, we can then apply the MASH_SEED phase adjustments to tune the output clock as necessary.

Thanks,

- Ken

over 7 years ago

0 Dean Banerjee over 7 years ago

TI__Mastermind 28011 points

Ken,

The LMX2592 gives no more phase synchronization capability than the LMX2594.

I appreciate your thoroughness in reading the datasheet (must be the SYNC flowchart) as indeed Fout%Fosc <>0, and this indicates that this is category 3.

But in fact, you found an error in the chart. Category 2 means the SYNC timing pulse is not critical. If you think about this, even if the SYNC pulse was off by one OSCin cycle, the same phase relationship would remain between Fosc and Fout. So it would be more correct to say that (Fout%Fosc>0) AND (Fosc%Fout>0) for this condition. I will update the datasheet.

Regards
Dean

0 Dean Banerjee over 7 years ago in reply to Dean Banerjee

TI__Mastermind 28011 points

Ken

You clicked that this did not resolve the issue, but left no details or response

0 Ken White over 7 years ago in reply to Dean Banerjee

Prodigy 210 points

Dean,
Thanks for the quick response.

I'm confused:
Are you saying that Category 2 will now be defined such that: Fout%Fosc AND Fosc%Fout must both be GREATER than zero? Or was this a typo and Fout%Fosc must still be EQUAL to zero. If this was not a typo then only non-integer multiples of Fosc would qualify for Category 2.

I.e. for Fout = 600MHz: Fosc = 100MHz = 6%1 = 0 --> Category 3
Fosc = 200MHz = 6%2 = 0 --> Category 3
Fosc = 300MHZ = 6%3 =0 --> Category 3
Fosc = 400MHz = 6%4 = 2 --> Category 2
Fosc = 500MHz = 6%5 = 1 --> Category 2
Is this right?

However, if Fout%Fosc = 0 still applies for Category 2 what is the difference whether I divide my 1200MHz reference by 4 using an external input counter or divide the 1200MHz input by 4 using the PRE-R Divider? How does the Phase Detector know the difference? Even if the Pre-R and Post-R Dividers combine to give a divisor of 24, won't the resultant rising clock edge presented to the Phase Detector be closely aligned with the rising edge of Fosc minus some small propagation delay? If so, why wouldn't that still qualify us for Category 2?

Sorry for the long rant. I'm just trying to wrap my brain around how this part actually works and if I can somehow get it to satisfy a demanding customer's requirement.

How soon will it be before the revised data sheet is available?

Thanks again,

- Ken

0 Dean Banerjee over 7 years ago in reply to Ken White

TI__Mastermind 28011 points

Ken,

Think of it this way, when a sync pulse is applied, it is re-clocked to the closes OSCin cycle.

In category 2, it is necessary to sync the device, but it doesn't matter what OSCin cycle it is.

For category 3, it does matter what OSCin cycle.

Ignore all the circuitry between OSCin and Fout; this is what confuses/distracts people about category 2.

So if Fout%Fosc=0, this means that if I take any rising edge of Fout and compare to the closes rising edge of Fosc, I get the same value. So 300 MHz output with 100 MHz input satisfies this.

Likewise, if Fosc%Fout=0, this means that if I take any rising edge of Fout and compare to the closest risinge edge of Fosc, I get the same value, so 300 MHz output with 1200 MHz input satisfies this and should also be category 2.

Now if I have 100 MHz input and 101 MHz output, then the phase relationship between Fout and Fosc depends on which Fout cycle is chosen. So to make phase alignment between two parts here, it matters what Fosc cycle the SYNC happens on.

Regards,
Dean

0 Ken White over 7 years ago in reply to Dean Banerjee

Prodigy 210 points

Dean,
The good news is, I have been able to consistently lock the 600MHz output clock to the rising edge of the 1200MHz input clock. This seems to confirm that Fosc%Fout == 0 is a valid condition for deterministic phase lock (and hopefully, Category 2). However, I get reminded in the TICSPro GUI output window every time I enable VCO_PHASE_SYNC that:

“Device in SYNC Category 3 (Timed SYNC Required):
This is because the output frequency is not a multiple of the input frequency.
Also check the datasheet for limitations on the maximum input frequency.”

plus occasional reminders to set INPIN_IGNORE to 0 since Category 3 requires a timed hardware SYNC input.

Now that I have a reliable lock, I was hoping to make use of the phase adjust capability to give the customer some fine tuning, if required. However, Equation (5) on datasheet page 26 does not seem to apply as it did when I initially ran the EVM with the integral 100MHz oscillator as an input. With a MASH_SEED of 1 and a PLL_DEN of 24, it will phase shift left each time I write the MASH_SEED register until the count of 12 and then phase shift back to the right for another 12 and then repeat. I don't see it ever go over 180 degrees. I am using 2nd order delta sigma modulator, N_Divider = 16, IncludedDivide is 4 when VCO_PHASE_SYNC = 1.

Could this be a function of not really being in Category 2 or the GUI overriding the control registers to a Category 3 mode? Is it possible Equation (5) needs to be modified to deal with a Fosc%Fout == 0 condition? Or maybe it's just cockpit error.

I might be able to get by with just the initial phase lock, but fine phase adjustment would be extra icing on the cake.

Thanks again for all your help and suggestions,

- Ken

0 Dean Banerjee over 7 years ago in reply to Ken White

TI__Mastermind 28011 points

Ken,

Thank you for the feedback and I am glad that this works.

I will update TICSPro and the datasheet for this. What we do is queue up errors like these and get in one release, so maybe about a month before it actually shows up that Fosc%Fout is category 2.

As for the MASH_SEED erratic phase shifts when VCO_PHASE_SYNC==1, I have seen this and there are a few more restrictions. I don't have an elegant closed form solution to when the mash seed gives uniformly increasing function, but I'm planning to add this description for MASH_SEED and PHASE_SYNC used together.

There are several considerations when using MASH_SEED
• Phase shift can be done with a FRAC_NUM=0, but FRAC_ORDER must be greater than zero. For
FRAC_ORDER=1, the phase shifting only occurs when MASH_SEED is a multiple of PLL_DEN.
• For the 2nd order modulator, PLL_N≥45, for the 3rd order modulator, PLL_N≥49, and for the fourth order
modulator, PLL_N≥54.

When using MASH_SEED in the case where IncludedDivide>1, there are several additional considerations in
order to get the phase shift to be monotonically increasing with MASH_SEED.
• It is recommended to use MASH_ORDER <=2.

When using the 2nd order modulator for VCO frequencies below 10 GHz (when IncludedDivide=6) or 9 GHz
(when IncludedDivide=4), it may be necessary to increase the PLL_N value much higher or change to first
order modulator. When this is necessary depends on the VCO frequency, IncludedDivide, and PLL_N value.

REgards,
Dean

0 Ken White over 7 years ago in reply to Dean Banerjee

Prodigy 210 points

Dean,

I believe that I am already in compliance with your guidelines for MASH_SEED adjust when VCO_PHASE_SYNC = 1. FRAC_ORDER = 2, and PLL_N = 48. VCO Frequency is 9600, ChannelDiv = 16 and IncludedDivide = 4. Can you think of any other knobs I can turn to get 360 degrees of consistently increasing phase shifts?

Just to make sure I touch all the bases, I'd like to ask you about the LMX2592. In this case, the incremental phase delay adjustment was very consistent and I was hoping I could use it for this application because I could run the VCO down to 4800MHz. This gives me approximately 100mA less current drain than the LMX2594 at the same power level setting. Am I correct in assuming that since the LMX2592 does not have the SYNC function, it cannot be configured to provide a deterministic phase relationship with the input clock?

By the way, I believe that there is a precedence error with the Phase Shift Equation (1) in the LMX2592 data sheet , page 17:

Phase shift (degrees) = 360 × MASH_SEED × PLL_N_PRE / PLL_N_DEN / [Channel divider value] (1)

The double divide at the end without parentheses kind of threw me off for awhile. When I interpreted the equation as being similar to Equation (5) in the LMX2594 data sheet:

Phase shift (degrees) = 360 * (MASH_SEED / PLL_N_DEN) * (PLL_N_PRE / Channel divider value)

I got the phase shifting as expected.

Thanks again,

- Ken

0 Dean Banerjee over 7 years ago in reply to Ken White

TI__Mastermind 28011 points

Ken,

In regards to comparing the LMX2592 to LMX2594 datasheet, I think that they are equivalent and PLL_DEN and [Channel divider value] are both in the denominator and the rest of the stuff is in the numerator, but in any case, the LMX2594 one is more clear.

In regards to the phase shifting, I note that you are below 10 GHz. Recall the statement I am adding:

"When using the 2nd order modulator for VCO frequencies below 10 GHz (when IncludedDivide=6) or 9 GHz
(when IncludedDivide=4), it may be necessary to increase the PLL_N value much higher or change to first
order modulator. When this is necessary depends on the VCO frequency, IncludedDivide, and PLL_N value."

Now technically your included divide is 4 and you should be OK above 9 GHz, but this is a rule of thumb I found by playing with the part; I have no theoretical or design justification for this. So the only know I know of is to increase the N divider or decrease the modulator order to 1.

REgards,
Dean

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LMX2592: LMX2592 Phase Determinance