CDCM61001: Output differential clock waveform of amplitude is abnormal?

Bryan Huang

Intellectual 445 points

Part Number: CDCM61001

Hi Team

My customer check differential clock of waveform ,he think amplitude is too big,

he would like to know ,is this output result is normal?

Can you provide some suggestions? thx.

over 7 years ago

0 Noel Fung over 7 years ago

TI__Guru** 108340 points

Hi Bryan,

Do you have a schematic?
What kind of output format did the customer set?
Did it lock?
Where was the signal probed?
Please provide as much information as possible so that we can help brainstorming.

0 Bryan Huang over 7 years ago in reply to Noel Fung

Intellectual 445 points

Hi Noel:

What kind of output format did the customer set? 200MHz differential clock for DDR4 ref. clock.

Where was the signal probed? CDCM61001 IC output pin

Schematic:

0 Noel Fung over 7 years ago in reply to Bryan Huang

TI__Guru** 108340 points

Hi Bryan,

The values of R1245 - 1248 are not correct. The effective resistance should be 50Ω, right now is 500Ω.

These resistors should be placed closed to the receiving end. When you probe the signal, you should probe at the receiving end as well.

0 Bryan Huang over 7 years ago in reply to Noel Fung

Intellectual 445 points

Hi Noel:

Thanks for your reply.

My customer change the resistance to 100 ohm , is ok? or must be change to 50 ohm.

another question, Is this waveform normal?

0 Noel Fung over 7 years ago in reply to Bryan Huang

TI__Guru** 108340 points

Hi Bryan,

The waveform looks much better.

Did you change all four resistors to 100Ω?

What is the Vcm (common mode input voltage) of the receiver? From the schematic, the bias voltage is just 0.6V, is this intentional?

If Vcm is 1.2V, then use single 50Ω pull-up instead of voltage divider.

0 Bryan Huang over 7 years ago in reply to Noel Fung

Intellectual 445 points

Hi Noel:
Yes , all four resistors to 100 ohm.
My customer is depends on Xilink FPGA of design, their demo board of resistance is 1k ohm, they don't sure the 0.6V of reason.

therefore he want to know, are the four resistors mainly set to bias voltage?
Why is the resistance of 1K and 100 ohms causing such a large difference in the output waveform?
And how is TI calculating the effective resistance?
he want to know how this is calculated?

0 Noel Fung over 7 years ago in reply to Bryan Huang

TI__Guru** 108340 points

Hi Bryan,

Differential signaling and termination requirement can be found here: www.ti.com/.../snla187.pdf

Clock & timing

Clock & timing forum

CDCM61001: Output differential clock waveform of amplitude is abnormal?