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TPL5010: Unreliable WAKE timing

Jean-Christophe
Prodigy 80 points
Part Number: TPL5010

I am using the TPL5010 to trigger the power supply of an MCU.

When the MCU is done with its work it sends a pulse on the DONE pin of the TPL5010 and turns its power supply OFF (the TPL remains ON).

After the required delay (about 30s in our case with 16Kohm attached to pin DELAY/M_RST) the power supply is turned ON again thanks to the WAKE pulse issued by the TPL5010.

For the sake of testing the design we trigger the DONE pulse using a switch. Everything works well except that the WAKE pulse delay (after DONE is issued) is unreliable. It varies randomly from 14s to 28s.

Is there something that we overlooked in the datasheet and that could explain this situation? Any idea how to solve this problem?

The schematic below depicts the test implementation.

  • 0
    TI__Genius 16845 points

    I think there may be some confusion here about the timing produced by the device.
    The WAKE pin will produce a periodic output pulse, if a valid DONE pulse is received within the programmed time interval.
    The DONE input must be received within the programmed time interval (i.e. 30 seconds), or the device will output a RSTn pulse and the timer will reset.
    Therefore, there is not necessarily a concern with "WAKE pulse delay" from 14s to 28s.

    This is also addressed in my response on the other post. I'll link the threads here for reference:
    https://e2e.ti.com/support/clock_and_timing/f/48/p/718080/2649664#2649664
    https://e2e.ti.com/support/clock_and_timing/f/48/t/718085

    Kind regards,
    Lane

  • 0 in reply to Lane Boyd
    Prodigy 80 points
    Thanks Lane
    I understand. My mistake was that I was counting the FIRST delay from the time the FIRST DONE pulse was issued.

    But then, how do we determine this delay before the first WAKE pulse (first cycle only)?
    Is it counted since POR or rather t_R_EXT+POR?
    The datasheet says t_R_EXT is typically 100ms, so POR+t_R_EXT is negligeable compared to my 30s delay. I should get about the right timing for the first cycle...

    I understand RSTn is asserted LOW whenever there is a missed DONE. But my question relates to the first cycle only.
    On figure 1. (datasheet) it looks like RSTn is LOW for a time t_R_EXT+t_RSTn after power up. t_RSTn =320ms so again, that doesn't explain the erratic delay before the first WAKE pulse.

    Jean-Christophe
  • 0 in reply to Jean-Christophe
    TI__Genius 16845 points

    Hi Jean-Cristophe,

    After a POR event, the device first reads the external resistance for 100ms. Next, it holds RSTn low for 320ms until RSTn is set high and the timer begins.
    Therefore, you will observe the WAKE pulse in 30 seconds if a valid DONE pulse is received within t_IP (i.e. 30 seconds). Otherwise, you will see a pulse on RSTn.

    Kind regards,
    Lane

  • 0 in reply to Lane Boyd
    Prodigy 80 points
    Thank you very much Lane
    It was not so explicit in the datasheet. That clarifies the point.
    best regards
    Jean-Christophe