Prior to integrating the TPL5010 into a larger design I prepared a small schematic to test it.
In this situation I am using a push-button to produce the pulse on the DONE input in order to trigger the next WAKE pulse.
I set the DELAY/M_RST resistor to 16Kohm to get a theoretical WAKE pulse timing of about 30 seconds (not critical for the test).
I don't need the RSTn capability in my case so I left the pin unconnected. I also tried to connect a pull-up to VCC but didn't notice any change in overall result.
The schematic is as follows:
The problem is that the WAKE pulse is not triggered at a steady frequency, as it should. The delay between pulses varies from 8 s to 28 s when I was expecting a pulse every 30 seconds or so.
My understanding is that the DONE pulse triggers the counter for the first cycle. So shouldn't I expect the WAKE pulse 30 s after the DONE pulse (talking of the first cycle only). Then, for subsequent cycles the DONE pulse should be triggered within the tD_DONE delay (para 7.6 of the datasheet) and my understanding is that I should have periodic WAKE pulses every 30s.
Is there anything wrong with the schematic or/and with my interpretation of the datasheet?
