Other Parts Discussed in Thread: LMK04826, , LMK04832
We are trying to generate 800 MHz clock using a 120 MHz reference for PLL2. We use VCO0 at 2.4 GHz.
We observe the 2.4 GHz leaking to the power pin(VCC_VCO) at -38 dBm and at the CPOUT2 at -45 dBm. ( I have used 10 pFs on the bypass line caps)
However, if we switch to VCO1 ( changed the reference to 100 MHz) at 3 GHz, the level of leakage at the power pin and the CPOUT2 is -60 dBm.
Could you please explain? Is there a way to reduce the leakage?