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Multi-Device synchronization on multiple boards

Ken Hanson
Prodigy 70 points
Part Number: LMK04616
Other Parts Discussed in Thread: LMK04832

I would like to use the LMK04616 in a multi-chassis system, and synchronize them so a SYSREF signal in one chassis is synchronized to a SYSREF signal in a second chassis. My plan would be to distribute a copy of a reference clock to each chassis, taking care to equalize the phase at each chassis (or calibrate within the chassis for any phase difference). In each chassis the LMK04616 would be in dual PLL mode, receiving the reference clock at a CLKin pin. Can multiple LMK04616 ICs be synchronized in this way? If so, what constraints are required in selecting frequencies for reference clock, VCXO, SYSREF, and Device Clk?

I read the SNAU222 Multi-Device synchronization with the LMK04616, but it only discusses multiple devices on the same board.

I see how multiple LMK04832 devices could be synchronized as above if the reference clock is a submultiple of the SYSREF (because CLKout6 or CLKout8 are available at the feedback MUX of the first PLL). I don't see how to accomplish the same in an LMK04616, unless all dividers can be sync'd on an edge of the CLKin signal or an edge of the PPL1 phase detector input. The LMK04616 does not allow an output to feedback to the first PLL.

  • 0
    TI__Mastermind 28550 points

    Hi there,

    I see your point about the 0-delay to PLL2.

    Ken Hanson said:
    Can multiple LMK04616 ICs be synchronized in this way? If so, what constraints are required in selecting frequencies for reference clock, VCXO, SYSREF, and Device Clk?

    Note however that provided the first PLL has input frequency = GCD(input frequency, VCXO frequency), it will be in 0-delay too.  This is similar to a cascaded dual loop mode in the LMK04832.  This does result in two APLLs in series which can result in a bit more phase drift over PVT, however if multiple devices are used, they would drift together.

    I could take a closer look, but perhaps that above comment can help.  Let me know.

    73,
    Timothy

  • 0 in reply to Timothy T
    Prodigy 70 points

    I think I see a way to get deterministic phase relationships between the CLKin and the CLKout signals. When the LMK04616 receives a Sync to align the output clocks, are the /R & /N dividers for PLL2 initialized? If not, is there an alternative method provided to do that?

    Thanks.

  • 0 in reply to Timothy T
    Prodigy 70 points
    Assuming the /R & /N at PLL1 & PLL2 don't have simple power of 2 relationships, there can be multiple phase relationships when the PLLs are locked. I need to have a single deterministic relationship between the clocks at various points, especially CLKin compared to CLKout. This requires that the /R & /N at each PLL can be initialized. I believe the best performance would occur if initialization were synchronous with the leading edge of the PLL1 RefCLK.
  • 0 in reply to Timothy T
    Prodigy 70 points

    Assuming the conditions you give above, and I synchronize my Sync pulse rising edge to the CLKin rising edge, will the synchronized CLKout signals always have the same deterministic relationship to CLKin? This would allow multiple LMK04616 ICs on different boards to synchronize all CLKout signals across the system, based on the same reference applied to CLKin of each LMK04616.

  • 0 in reply to Ken Hanson
    Prodigy 70 points

    I see the validity of your answer. If the frequency relationships are correct, the edge of the OUTCLK used for feedback in PLL2 will line up with the edge of CLKin by the locking action of the PLLs. If the SYNC is pulsed close to the edge of CLKin, the OUTclk signals will be aligned to each other, and if that alignment moment is a bit different than the edge of CLKin, the locking action of the PLLs will bring the alignment moment of the CLKout signals into alignment with the CLKin.