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LMK03318: LMK03318 output configuration for 0.8V common mode bias

Robin Yu
Intellectual 2190 points
Part Number: LMK03318

1.The clock output is for FPGA GTH port. It is LVDS signal. The required common mode voltage for FPGA input is 0.8V. How to configure the output clock?

Below is the schematic of customer, is it OK?

2.In addition, could the input frequency of primary reference and secondary reference be different? Such as, 25MHz Oscillator for primary and 100MHz Oscillator for secondary.

Thanks.

  • TI__Genius 16845 points

    I reviewed the schematic, here is some feedback:

    • In general I recommend to use pull-up and pull-down resistors on the logic inputs (REFSEL, GPIOx, and HW_SW_CTRL)
    • If frequency margining will not be used, pull GPIO4 high
    • What are the input and output frequencies? C602 has been set to 3.3nF, the recommended value for the PLL operating in integer mode


    A1. To configure for LVDS output clock with 0.8V common-mode, the output termination network requires some modification. If you will generate the common-mode voltage from VCC_1.2V:

    • Remove the pull-up and pull-down from OUTx_P for each output
    • Replace the pull-up on OUTx_N with 2.5K
    • Replace the pull-down on OUTx_N with 5K
    • Place a 100-ohm differential load resistor at the reciever


    A2. It is OK to use a different frequency for PRIREF and SECREF, but only one oscillator should be enabled at a time. It is not recommended to drive both input simultaneously because there will be coupling between inputs; we can assume the inputs will have a small PPM offset because they are separate oscillators.

    Kind regards,
    Lane

  • in reply to Lane Boyd
    TI__Intellectual 2190 points

    Hi Lane,

    Thanks for quick response.

    Will feedback to you after checking with customer.

    Robin

  • in reply to Lane Boyd
    TI__Intellectual 2190 points
    Hi Lane,

    Want to double confirm with you.
    1. Just need to add pull-up and pull-down resistor at OUTx_N, and no resistor for OUTx_P? Why not both P and N port?
    2. There is no 2.5k and 5k resistor for mass production, is this resistor selection flexible? such as 5k, 10k?
    3. The 100Ohm for differential input has already integrated in FPGA, so we need remove it in the external components. Correct?
    Thanks.

    Robin
  • in reply to Robin Yu
    TI__Genius 16845 points
    Hi Robin,

    A1. You don't need to add the pull-up and pull-down resistors on OUTx_P because the 100-ohm differential load termination at the receiver will cause the bias to shared. Consider the Thevenin equivalent circuit at DC.
    A2. Yes, 5K and 10K are OK.
    A3. If the receiver has integrated load termination, you do not need to place the external 100-ohm load.

    Kind regards,
    Lane