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Original question:

part on cdce72010 EVM board

part on cdce72010 EVM board

Venkatesh ponduri
Prodigy 45 points
Other Parts Discussed in Thread: CDCE72010

What is the alternate partnumber for VCXO. Because TCO-2111T part is not available. Kindly suggest us any VCXO?????.

For 960MHz input VCXO, 60MHz output  and 10MHz primary reference. what are the register settings???

  • 0
    Prodigy 45 points
    Hi,
    I am venkatesh, Question is regarding CDCE72010 lock status pin
    The following are the inputs

    1. Primary 10MHz Kept setting as LVPECL
    2. VCXO 960MHz Kept setting as LVPECL



    All the outputs are 60MHz


    Register Setting are

    X"EA3C0250",
    X"EB0C0001",
    X"EB0C0002",
    X"EB0C0003",
    X"EB0C0004",
    X"EB0C0005",
    X"EB0C0006",
    X"EB0C0037",
    X"EB0C0018",
    X"68000C09",
    X"BB8407EA",
    X"8000418B");



    problem is i am getting output 60MHz (not exact 60MHz and value is 59.995MHz) in all the output channels. But i am not getting Lock. I have Satisfied the Condition

    Frequency (VCXO_IN or AUX_IN) / Frequency (PRI_REF or SEC_REF) = (P*N)/(R*M)
    by putting P=1, N= 125, R=1, M= 12000.


    Could please suggest the changes needed in register setting??????. Reply as soon as possible ???
  • 0 in reply to Venkatesh ponduri
    TI__Mastermind 32575 points

    What is your 960 MHz VCXO part number?   Can you share its datasheet?

    If you only only need 60 MHz output, it would probably be easier and cheaper to select a VCXO (LVCMOS) with lower frequency like 60 or 120 MHz.

    Once you select a VCXO, you can use the PLL loop filter calculator tool to design the loop filter and use CDCE72010 GUI to generate the register settings.  

    Loop Filter Calculator:

    Control GUI:

    For your reference, I attached an example loop filter calculator spreadsheet that achieves a stable PLL Loop BW of ~100 Hz (phase margin ~ 75 deg) with REF frequency = 10 MHz, PFD frequency = 1 MHz, and VCXO frequency = 60 MHz (PLL dividers are R = 1, M = 10, P = 1, N = 60).

    CDCE72010_PLL_Calculation_V1.08_10M-ref_60M-vcxo_100Hz-pllBW.xls

    Alan

  • 0 in reply to Alan O
    Prodigy 45 points

    sch file.rarHi Alan, Thank you for your reply. Here I have used VCXO is 960 MHz (LVPECL) and primary 10 MHz (LVDS).  3 Outputs are 60 MHz, three output are 180 MHz. Kindly check the attached Schematics file.kindly review the schematics. R285, R288 are NC

  • 0 in reply to Venkatesh ponduri
    TI__Mastermind 32575 points

    I think the schematic looks OK.  See the attached Excel file which has suggested PLL dividers and Charge pump settings based on your current external loop filter components and 960 MHz VCXO to design the PLL bandwidth ~128 Hz with phase margin ~70 deg and PFD frequency = 250 kHz.  It assumes the VCXO has +/-100 ppm (200 ppm APR overall).

    CDCE72010_PLL_Calculation_V1.08_10M-ref_960M-vcxo_128Hz-pllBW.xls

    Since you did not provide it, I search the VCXO datasheet and referenced this one:

    Alan