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LMK04610: About jitter of clock distribution mode

beast band
Prodigy 30 points
Part Number: LMK04610

Hi,

I would like to know about the accumulate jitter of CLKoutX if I use LMK04610 in clock distribution mode.

How much jitter from MUX and clock output block contribute, 100MHz input frequency (from LMK61xx) at CLKinX and 16-bit divider range is 1000 - 65535. 

Best Regards,
Beast

  • 0
    TI__Mastermind 32575 points
    The additive phase noise floor is around -165 dBc/Hz at 122.88 MHz. It should be similar for 100 MHz. This assumes your differential input slew rate is at least 3 V/ns.

    Alan
  • 0 in reply to Alan O
    Prodigy 30 points

    Hi Alan,

    Thank you for your reply, but I have a few questions to ask.

    1. Is the –165 dBc/Hz Noise Floor at 122.88 MHz in datasheet a condition in PLL1 and PLL2 is enable ?

    2. In ideal divide down frequency by 2 phase noise is better by 6dB, if i would like to use CLKout at frequency 122.88MHz/2^12

    (from TICS Pro output stage divide by 8 is default to obtain 122.88MHz --> change to divide by 2^15) phase noise would better by 72dB

    that I think it limit by noise of divider or internal circuits before reach 72dB better, is it correct ?

    3. If 2 is correct, what is noise floor of this condition ?

    Thank,

    Beast

  • 0 in reply to beast band
    TI__Mastermind 32575 points
    -165 dBc/Hz noise floor is measured at 20 MHz offset, so only the buffer noise floor contributes at this offset (PLL1 and PLL2 noise contribution are not present at this offset). Since the -165 dBc/Hz is the phase noise *floor*, this noise will not scale down with frequency much below this value. This is due to divider/buffer thermal noise floor, which is broadband and virtually flat with frequency.

    Alan