Hello, I am trying to understand the SPI -3 wire timing diagram.
For a read command is the command automatically latched into the shift register after the 16th bit with the read data then being available for the next 8 clock cycles on the SDIO pin? or does a full 24bit command need to be sent followed by asserting CS followed by an additional 8 clock cycles to read the data?
An example of a read sequence would be nice.
Thank you.
