Hello,
Our customer use the CDCI6214 for Ref CLK of PCIe Gen2.
They want to check the characteristics of Phase noise and Jitter.
Do you have the typical characteristics of the output phase noise and jitter?
(25MHz input and 100MHz HCSL output)
May I ask the specification of the PCIe?
There are three specs. of jitter on the PCIe specification.
1) Trefclk-HF-RMS 1.5MHz< f < 50MHz limit is 3.1ps rms
2) Trefclk-SSC-RES limit is 75ps pp
3) Trefclk-LF-RMS 10kHz< f < 1.5MHz limit is 3.0ps rms
---- question 1 -----
The test of 1) and 3) Is it a value obtained by integrating frequencies 1.5MHz to 50MHz and
10kHz to 1.5MHz ?
---- question 2 -----
Do the test of 1) and 3) with stop the SSC function?
Best Regards,
Naoki Aoyama
