With SPI clock and data, is it permissible to do as 32-bit shift and then raise LE, in which case only the last 24 bits are significant?
This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
With SPI clock and data, is it permissible to do as 32-bit shift and then raise LE, in which case only the last 24 bits are significant?
Michael,
I do not think this will work with this device.
For this device, you send the address first, and then the data. When you pull CSB high, then it signals the end of the register and then I guess the next thing expected is an address.
I know this trick worked for our other LMX devices with microwire, but that's because the address was at the end of the word, not the beginning.
Regards,
Dean
I am hanging on your "I guess" - which makes me wonder how sure you are?! To answer my question I think an understanding of the circuit inside is required. But if it is a 24-bit serial-in parallel-out shift-register and clocking in 32 bits then the first 8-bits would simply get shifted out the other end leaving the most-significant 24 bits in the register which then gets parallel loaded into the internal register according to address bits on the rising edge of LE (CSB). I cannot think of any way shifting 32 bits in would do otherwise, but please correct me. Of course if I build a board with LMX2592 populated then I can answer my question the hard way, but I am not yet in a position to do this (a prototype board with Rogers substrate is not cheap!)