• State TI Thinks Resolved
  • Locked Locked
  • Replies 7 replies
  • Answers 2 answers
  • Subscribers 21 subscribers
  • Views 907 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

CDCLVC1104: Input slew rate

Oba
Genius 17355 points
Part Number: CDCLVC1104
Other Parts Discussed in Thread: CDCV304, LMK00105

Hello,

 

I have a question about input slew rate.

 

CDCLVC1104 datasheet defines “input slew rate” as 1(MN) and 4(MAX) V/ns.

Now a customer is looking at some crystal oscillators, but they find it is difficult to satisfy both MIN and MAX.

They can satisfy MAX value by reducing load capacitance value, but doing that brings MIN value can’t be satisfied

including tolerance by temperature and voltage drift.

My question is that do you have any recommended crystal oscillator to satisfy this requirement?

 

Regards,

Oba

 

  • 0
    TI__Mastermind 28560 points
    Hello Oba,

    Yes, the min spec a 1 V/ns is relatively high. I was looking at some XO datasheets and found the ones I looked at to fall short. I did find some Crystek VCXO C33xx model, which has 2 ns max 20% to 80% output spec for oscillators >= 80.10 MHz. Assuming 3.3 V output, 0.6 * 3.3 V / 2 ns = 0.99 ns/V which is very as close to the specification. I'm sure the typical value for rise time on this device would be more than ok, but understand this is technically violation of the datasheet.

    My experience is that while at some point slower slew rates break an input, but typically it is just an impact to the noise floor. For example the LMK0482x device specifies a minimum of 0.15 V/ns, but a typical of 0.5 V/ns with a note that values below the typical can result in reduced of performance.

    --

    Have you considered the LMK00105 or CDCV304?

    73,
    Timothy
  • 0 in reply to Timothy T
    TI__Genius 17355 points

    Hello Timothy,

     

    I’m very sorry, I found a big mistake in my question.

    I mixed up slew rate and rise/fall time. Small value of slew rate means slow rise/fall time. I thought in reverse when I posted yesterday.

     

    What I wanted to ask is that they can satisfy MIN value(=slow) by reducing load capacitance value, but by doing that it will be over MAX value (=too fast)

    Including tolerance by temperature and voltage drift.

    What do you think?

     

    Regards,

    Oba

  • 0 in reply to Oba
    TI__Mastermind 28560 points
    Hello Oba,

    I think that the 1 V/ns to 4 V/ns is a fairly wide range and wouldn't cause trouble as far as removing some cap and being too fast, a 4 V/ns is pretty fast. Given a 3.3 V signal from 20% to 80%, 1 V/ns to 4 V/ns means rise times from 1.98 ns rise time to 0.495 ns rise time.

    It's interesting about the max spec, typically higher is always better. The only reason I can see to limit slew rate is that with faster edges you will have higher odd harmonic content.

    I don't think your issue is likely to be with the 4 V/ns max, but with the 1 V/ns minimum.

    73,
    Timothy
  • 0 in reply to Timothy T
    TI__Genius 17355 points

    Hello,

    Sorry for my late reply.
    I checked again and confirmed MAX value, 4V/ns, is the problem.
    Anyway, do you have any recommended crystal oscillator part number to meet this input specification?

    Regards,
    Oba

  • 0 in reply to Oba
    TI__Mastermind 28560 points
    Hello Oba,

    I'll see what I can find. What frequency is required?

    73,
    Timothy
  • 0 in reply to Timothy T
    TI__Genius 17355 points
    Hello,

    24MHz and 65.536MHz are required.

    Regards,
    Oba
  • 0 in reply to Oba
    TI__Mastermind 28560 points
    Ok thanks, I'll let you know what I find out.

    73,
    Timothy