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Self-offset Phase Locked Loop

Thomas Noonan
Prodigy 140 points
Other Parts Discussed in Thread: LMX2571

Has anyone worked with a Self-offset Phase Locked Loop?  I've read several articles on them and have seen multiple reference to them but have not found anything from someone who has built one.  I was thinking of using one to generate a fixed LO but when I made a rough prototype by connecting several small evaluation boards together my phase noise was much higher then a conventional PLL.  I was not expecting the 14 dB improvement that theory says I should get due to my set up but thought I would see some improvement.

If anyone has experience with Self-offset Phase Locked Loops I would appreciate any insight you could give.

  • 0
    TI__Mastermind 28031 points

    Thomas,

    I have not personally built one of these self-offset PLLs, but I have talked to others who successfully have.

    The concept is to have a higher frequency, Fvco, and then mix it down by by a fixed frequency, Fif, down to some tunable frequency Flo.  As Fif is a fixed frequency, the VCO tuning range can be very narrow and the assumption is the VCO is really good.

    In theory, if the mixer is perfect and the Flo frequency is noiseless, the  N divider value can be reduced and there is a huge theoretical gain.  The mixer might add some noise, but the big thing is that whatever frequency you mix it down with has to be super good.  

    My suspicion is that whatever fixed frequency, Fif, you are using may be dominating your phase noise..

    Regards,
    Dean

  • 0 in reply to Dean Banerjee
    Prodigy 140 points

    Dean,

    As always thank you for your quick reply.

    From your reply I'm not sure if you are referring to a frequency offset PLL where an LO from a separate source is used to mix with the output from the VCO to lower the frequency feed back to the phase detector thereby lowering the N.  Or a Self-offset PLL where the VCO output is divided down by 2 separate dividers then mixed to lower the frequency as shown below.  This was presented by Bogdan Sadowski in his article "A Self-offset Phase-locked Loop". The link to the article is

    www.microwavejournal.com/.../6076-a-self-offset-phase-locked-loop

    I believe a good part of my issues are with isolation since the prototype is made up of several small boards connected with coax and the DC power is from bench supplies and external wires.  I am in the process of creating prototype PCB that should help with this but would still appreciate input from anyone who may have worked with this type of design before.  Would it be possible for you to pass my contact information to some of the people you mentioned have already built a self-offset loop.

    Thank You Again

    Tom

  • 0 in reply to Thomas Noonan
    TI__Mastermind 28031 points
    Tom,

    What I was talking about was the first case, where an LO from another source is used to mix down the VCO frequency. Maybe not exactly the same thing.

    I have been working with our LMX PLLs for a long time now and don't know of anybody who has done this style of PLL (except you). Not saying it hasn't been done, but I don't know anybody who does, but if so, they are free to give their input.

    Regards,
    Dean
  • 0 in reply to Dean Banerjee
    Prodigy 140 points

    Dean,

    Not the answer I was hoping for but Thank you for your quick reply.  I'd like to keep this question open for awhile so hopefully someone else in the group can provide some input.

    I also have a follow up question on calculating the Flicker and Flat noise for a frequency offset  PLL which I believe will also apply to the self-offset PLL. I'll use an example to try and clarify my question.

    With a standard PLL using a LMX2571, a 100 MHz reference (R=1), and a 2000 MHz VCO. Using the FOMs from the LMX2571 data sheet

    PN(flat) =-231

    PN(1/f) = -124

    I can calculate my Flat and Flicker noise as follows

    PLL(flat) = PN(1hz) + 20LOG N +10LOG f(pd)

    PLL(flat) = -231 +20LOG 20 + 10LOG 100*10^6

    PLL(flat) = -231 + 26 + 80

    PLL(flat) = -125

    I'll calculate the Flicker noise at 10 KHz offset

    PLL(1/f) = PN(10khz) - 10LOG(offset/10K) + 20LOG(fo/1GHz)

    PLL(1/f) = -124 -10LOG(1) + 20LOG(2)

    PLL(1/f) = -124 - 0 + 6

    PLL(1/f) = -118

    This agrees with the results from PLLatinum Sim

    Now if I use a frequency offset PLL where I take a very clean 1500 MHz external signal  to mix with the 2000 MHz VCO I can feed the difference frequency of 500 MHz back to the phase detector giving me an effective N of 5.

    My question is for the Frequency offset PLL do I use an N of 5 or 20 when calculating the Flat noise and like wise do I use 2000 MHz or 500 MHz for the fo when calculating the Flicker noise.

    Thank you again for all your help,

    Tom

  • 0 in reply to Thomas Noonan
    Prodigy 140 points
    Dean,

    Another follow up question. The LMX2571 data sheet shows that the Total phase noise from the Flat and Flicker noise is the voltage sum of the two. But it looks like PLLatinum Sim calculates the RMS sum of the two values. Which do you consider correct?
    Thanks,
    Tom
  • 0 in reply to Thomas Noonan
    TI__Mastermind 28031 points
    Tom,

    1. I don't have any experience with offset phase locked loops nor do I know anybody in my group, and I have been here for quite some time now. I think that the thread automatically closes after a while, but this does not stop someone from responding to it.

    2. For the LMX2571, if you mix down with a perfect 1500 MHz, then you would an N divide of 5. Only thing is that you need to make sure the PLL N can go this low. According to TICSPro, minimum N is 6 in integer mode. Anyways, if it was possible, you would use a PLL_N=5 and the flat noise would theoretically improve 20*log(2000/500) = 12 dB.

    Likewise, the pll 1/f (flicker) noise I would expect to improve by 20*log(2000/500) = 12 dB

    3. As for adding the flat and flicker noise, it should be the RMS sum as in PLLatinum Sim. The flat noise is not correlated to the flicker noise, so it adds in an RMS sense.

    Regards,
    Dean
  • 0 in reply to Dean Banerjee
    Prodigy 140 points

    Dean,

    Thank You for all your help.

    Tom