LMK04828: Simulating LMK04828 with FPGA hdl model

Hello,

I'm not very familiar with hdl, but from I quickly read, I'm not sure how it would help here?

For generating a register map to do what you want, I'd recommend download the TICS Pro software (TICSPRO-SW).  It's for programming our EVMs or generating a register map for your own implementation.

user5854578 said:

I basically want to assign oscout/clkin(2) to be my input clock which supplies feedback to sdclkout(3) and dclkout(4).

I'm a bit confused on what you mean by apply feedback to SDCLKout3 & DCLKout4.  OSCout/CLKin2 can be used as an input to the first PLL when the device is acting in dual loop mode.  Refer to section 9.4.1 of datasheet.

user5854578 said:

Furthermore I want to take the 3GHz VCO and output 1.5GHz on clkout (0), (8) and (10).

You will need to provide a reference to OSCin.  If you are using single loop.  In TICS Pro...

On the CLKin and PLLs page..

• change the OSCin Source to Independent. [although based on your description you may need to use dual loop mode?  So external VCXO may be what you need]
• Type in your OSCin frequency.
• Set your doubler/R divider to produce a phase detector frequency <= 155 MHz.
• Set your PLL2 N Divider and N prescaler to enable 3 GHz.  You can also type 3000 into the VCO/clock distribution frequency box on the right hand side.
• If you type in 3000 MHz for VCO frequency, and then it changes to a non-3000 MHz number.  You need to adjust your doubler, PLL2 R divider, or PLL2 N prescaler (PLL2_P) to allow the equation here to be solved for 3000 MHz:  OSCin Freq / * (1 or 2 for doubler) / PLL2 R * PLL2_N * PLL2_P = VCO Frequency of 3000 MHz.
• Be sure to select VCO1 for your active VCO to achieve 3000 MHz range.

Now the the Clock Outputs page you can configure the output formats as required and the output dividers as required.

If you need dual loop mode, you're basically repeating this process but starting with a CLKin frequency, and solving for the VCXO frequency which will be the feedback for PLL1 (via PLL1 N) but also the reference to PLL2.

user5854578 said:

With regards to pins 59 & 58 (clkin_sel) I don't know what selects clkin(2).

If you want to select CLKin2 for input to the dual loop PLL, it can be as simple as setting CLKin_SEL_MODE = 0 (CLKin0 Manual).  If you want to use pin control, you must set (top right of CLKin and PLLs page)

• CLKin_SEL_MODE = (0x03) Pin Select Mode
• CLKin_SEL0 & 1 as input (with or without pull-up or pull-down).  Any CLKin_SEL pin not configured for input is considered as 0.
• Optionally you can invert the polarity of the input with CLKIN_SEL_POL.
• Because the software doesn't know the state of the input pins, you can set the "Selected Clock Input for PLL1" to CLKin2 so that frequency calculations in the software will be correct.

Section 9.3.5 Input Clock Switching contains table 4 which shows CLKin1_SEL = High & CLKin0_SEL = Low to make CLKin2 the active clock.

...

If you want to pass an input signal straight to the outputs, distribution mode is supported from CLKin1.  If you want to pass an input straight to the outputs while using single or dual loop mode.  It is possible to route CLKin0 directly to the SDCLKoutY outputs on the SYNC/SYSREF path as shown in figure 13 of the datasheet.  This latter mode can automatically be setup from the Set Modes page of LMK04828 by clicking the CLKin0 drives SYNC/SYSREF direct button.  Be sure to read section 9.3.1 about SYNC/SYSREF for other details for using the SYNC/SYSREF path so you don't inadvertently SYNC output clock output dividers.

73,
Timothy

Hello Wes,

user5854578 said:

Why set phase detector to 155MHz?

The reason you would set a high phase detector frequency is to reduce the noise contribution of the PLL.  The higher the phase detector frequency, the lower the noise contribution of the PLL.  Take a look at the presentation Choosing PLL Loop Bandwidths located at in the E2E Clock & Timing files section.  I think it's slide 17 which shows optimized RMS jitter values from 12 kHz to 20 MHz for different phase detector frequencies assuming an ideal reference.

In reply to user5854578:

spec says PLL1 Phase Detector Frequency max is 40MHz according to electrical properties

This is for PLL1.  For PLL2 it is 155 MHz.  When using PLL1 to do jitter cleaning, we often choose a smaller, say 1 MHz phase detector frequency because we are designing our loop filter with narrow loop bandwidths (say 10 to 200 Hz) and the lower phase detector frequency helps with capacitor size.  Any noise the PLL would have generated because of the lower phase detector frequency is cleaned by the VCXO of the dual loop architecture.

user5854578 said:

On the dev board I was able to generate a vco0 of ~2400, when fed through a 16 divider this gives ~150MHz.

This sounds good.  2400 MHz is in the VCO0 frequency band of LMK04828.

user5854578 said:

I’m confused because I through I was supposed to program from 0 up to top reg and not need to go back and tweak other registers subsequently.

Also, to enable certain functionality like JESD204B, you will need to do some subsequent programming.  Because the SYNC/SYSREF are shared, you can't get everything programmed as you need to in one go.  Refer to the JESD204B example of enabling SYSREF in 9.3.2.

user5854578 said:

When loading the device with vco mux set to vco1 and then subsequently changing once pll1 is locked to vco0 everything works, however if I leave vco mux set to vco0 and attempt load device the lmk04828bevm pumps out 170MHz instead of 150MHz.

PLL1 is traditionally used with an external VCXO connected to OSCin.  CLKinX will provide a reference to PLL1 and the VCXO the feedback via OSCin.  This is the jitter cleaning PLL in the dual loop mode.

PLL2 is traditionally used with one of the internal VCOs (external also possible).  OSCin will provide a reference to PLL2 and the selected VCO feedback internally or via CLKin1 if using external VCO.  It is provided a clean reference and it does frequency multiplication to get you the frequencies you want.  Note, if you could achieve all the frequencies you want with the VCXO frequency, you could run PLL2 in external VCO mode and the reference to OSCin for best performance.

So to best answer your question, I would need to know a higher level what your inputs are and your intention for single or dual loop, in which case I'd need to know your VCXO frequency.

But in general, if you change the VCO_MUX, they you will need to re-program the dividers to make the input frequencies lock the VCO in the proper frequency range.  At a minimum programming the PLL2_N register in 0x166, 0x167, and 0x168 to trigger the re-calibration.

73,
Timothy