I'm using the LMK in dual-loop mode and have successful lock on both PLL1 and PLL2. With VCO1 @ 3 GHz, I have no problem outputting clocks from 100 MHz to 500 MHz (divider values of 30 to 6). Once I try to go up to 1 GHz with a divider of 3, I no longer get an output. Any ideas why I can't output a 1 GHz clock but I can do lower frequencies?
Here is my relevant VHDL:
constant CLK_PWRDOWN: std_logic_vector(7 downto 0) := x"F9"; -- powers down both the device clock and sys ref clock output, see Table 16 of LMK04828 datasheet
constant CLK_DIV100M: std_logic_vector(7 downto 0) := x"7E"; -- Divide value of 0x1E, or 30. For VCO1 = 3000 MHz, produces an output of 100 MHz. Also includes ODL/IDL setting of 1
constant CLK_DIV200M: std_logic_vector(7 downto 0) := x"6F"; -- Divide value of 0x0F, or 15. For VCO1 = 3000 MHz, produces an output of 200 MHz. Also includes ODL/IDL setting of 1
constant CLK_DIV300M: std_logic_vector(7 downto 0) := x"6A"; -- Divide value of 0x0A, or 10. For VCO1 = 3000 MHz, produces an output of 300 MHz. Also includes ODL/IDL setting of 1
constant CLK_DIV375M: std_logic_vector(7 downto 0) := x"68"; -- Divide value of 0x08, or 8. For VCO1 = 3000 MHz, produces an output of 375 MHz. Also includes ODL/IDL setting of 1
constant CLK_DIV500M: std_logic_vector(7 downto 0) := x"66"; -- Divide value of 0x06, or 6. For VCO1 = 3000 MHz, produces an output of 500 MHz. Also includes ODL/IDL setting of 1
constant CLK_DIV1GIG: std_logic_vector(7 downto 0) := x"63"; -- Divide value of 0x03, or 3. For VCO1 = 3000 MHz, produces an output of 1000 MHz. Also includes ODL/IDL setting of 1
constant CLK_DIV1500M: std_logic_vector(7 downto 0) := x"62"; -- Divide value of 0x02, or 2. For VCO1 = 3000 MHz, produces an output of 1500 MHz. Also includes ODL/IDL setting of 1
constant CLK_EN : std_logic_vector(7 downto 0) := x"F1"; -- Delay features disabled, SYSREF output disabled, device clock output enabled
constant DCLK_LVPECL: std_logic_vector(7 downto 0) := x"06"; -- SYSREF power down, Device Clock LVPECL 2Vpp, Normal Polarity
constant DCLK_LVDS : std_logic_vector(7 downto 0) := x"01"; -- SYSREF power down, Device Clock LVDS, Normal Polarity
constant CLKIN0_EN : std_logic_vector(7 downto 0) := x"0A"; -- Enables CLKIN0 input and sets it to Bipolar (recommended for differential input)
constant CLKIN0_PLL1: std_logic_vector(7 downto 0) := x"0E"; -- This sets the reference clock for PLL1 to be the clock present on CLKIN0 input pin
constant SET_LOS0 : std_logic_vector(7 downto 0) := x"0B"; -- Sets the CLKIN0SEL pin to an output that will provide the Loss-of-Signal (LOS) status of CLKIN0
constant SET_MISO : std_logic_vector(7 downto 0) := x"33"; -- Sets the CLKIN1SEL pin to an output that will provide SPI readback of LMK registers
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--LMK register lookup table, 100MHz version
LMK_reg_proc: process (all)
begin -- |W1,W0,A12|A11-A0 | Data |
case Reg_ptr is -- R/W | | | |
when x"00" => LMKRegData <= SPI_R_nW & b"000" & x"000" & x"80"; -- Reset, Spi_3wire_dis (init)
when x"01" => LMKRegData <= SPI_R_nW & b"000" & x"000" & x"10"; -- Reset, Spi_3wire_dis
when x"02" => LMKRegData <= SPI_R_nW & b"000" & x"002" & x"00"; -- Powerdown
-----------------------------------------------------------------
--- Transceiver Quad 0 Reference Clock Settings -----------------
-----------------------------------------------------------------
when x"03" => LMKRegData <= SPI_R_nW & b"000" & x"100" & x"03"; -- Clkout0-1_odl, Clkout0-1_idl, Dclkout0_div, Table 16
when x"04" => LMKRegData <= SPI_R_nW & b"000" & x"101" & x"55"; -- Dclkout0_ddly_cnth, Dclkout0_ddly_cntl, Table 17
when x"05" => LMKRegData <= SPI_R_nW & b"000" & x"103" & x"00"; -- Dclkout0_adly, Dclkout0_adly_mux, Dclkout0_mux, Table 18
when x"06" => LMKRegData <= SPI_R_nW & b"000" & x"104" & x"00"; -- Dclkout0_hs, Sdclkout1_mux, Sdclkout1_ddly, Sdclkout1_hs, Table 19
when x"07" => LMKRegData <= SPI_R_nW & b"000" & x"105" & x"00"; -- Sdclkout1_adly_en, Sdclkouty_adl1, Table 20
when x"08" => LMKRegData <= SPI_R_nW & b"000" & x"106" & CLK_PWRDOWN; -- Dclkout0_ddly_pd, Dclkout0_hsg_pd, Dclkout0_adlyg_pd, Dclkout0_adly_pd, Dclkout0-1_pd, Sdclkout1_dis_mode, Sdclkout1_pd, Table 21
when x"09" => LMKRegData <= SPI_R_nW & b"000" & x"107" & x"00"; -- Sdclkout1_pol, Sdclkout1_fmt, Dclkout0_pol, Dclkout0_fmt, Table 22
-----------------------------------------------------------------
--- Transceiver Quad 2 Reference Clock and PF SYSREF2 Settings --
-----------------------------------------------------------------
when x"0a" => LMKRegData <= SPI_R_nW & b"000" & x"108" & CLK_DIV100M; -- Clkout2-3_odl, Clkout2-3_idl, Dclkout2_div, Table 16
when x"0b" => LMKRegData <= SPI_R_nW & b"000" & x"109" & x"55"; -- Dclkout2_ddly_cnth, Dclkout2_ddly_cntl, Table 17
when x"0c" => LMKRegData <= SPI_R_nW & b"000" & x"10b" & x"00"; -- Dclkout2_adly, Dclkout2_adly_mux, Dclkout2_mux, Table 18
when x"0d" => LMKRegData <= SPI_R_nW & b"000" & x"10c" & x"00"; -- Dclkout0_hs, Sdclkout1_mux, Sdclkout1_ddly, Sdclkout1_hs, Table 19
when x"0e" => LMKRegData <= SPI_R_nW & b"000" & x"10d" & x"00"; -- Sdclkout3_adly_en, Sdclkouty_adl3, Table 20
when x"0f" => LMKRegData <= SPI_R_nW & b"000" & x"10e" & CLK_EN; -- Dclkout2_ddly_pd, Dclkout2_hsg_pd, Dclkout2_adlyg_pd, Dclkout2_adly_pd, Dclkout2-3_pd, Sdclkout2_dis_mode, Sdclkout2_pd, Table 21
when x"10" => LMKRegData <= SPI_R_nW & b"000" & x"10f" & DCLK_LVDS; -- Sdclkout3_pol, Sdclkout3_fmt, Dclkout2_pol, Dclkout2_fmt, Table 22
-----------------------------------------------------------------
--- HSADC1 Sample Clock and SYSREF Settings ---------------------
-----------------------------------------------------------------
when x"11" => LMKRegData <= SPI_R_nW & b"000" & x"110" & x"03"; -- Clkout4-5_odl, Clkout4-5_idl, Dclkout4_div, Table 16
when x"12" => LMKRegData <= SPI_R_nW & b"000" & x"111" & x"55"; -- Dclkout4_ddly_cnth, Dclkout4_ddly_cntl, Table 17
when x"13" => LMKRegData <= SPI_R_nW & b"000" & x"113" & x"00"; -- Dclkout4_adly, Dclkout4_adly_mux, Dclkout4_mux, Table 18
when x"14" => LMKRegData <= SPI_R_nW & b"000" & x"114" & x"00"; -- Dclkout4_hs, Sdclkout5_mux, Sdclkout5_ddly, Sdclkout5_hs, Table 19
when x"15" => LMKRegData <= SPI_R_nW & b"000" & x"115" & x"00"; -- Sdclkout5_adly_en, Sdclkouty_adl5, Table 20
when x"16" => LMKRegData <= SPI_R_nW & b"000" & x"116" & CLK_PWRDOWN; -- Dclkout4_ddly_pd, Dclkout4_hsg_pd, Dclkout4_adlyg_pd, Dclkout4_adly_pd, Dclkout4-5_pd, Sdclkout5_dis_mode, Sdclkout5_pd, Table 21
when x"17" => LMKRegData <= SPI_R_nW & b"000" & x"117" & x"00"; -- Sdclkout5_pol, Sdclkout5_fmt, Dclkout4_pol, Dclkout4_fmt, Table 22
-----------------------------------------------------------------
--- HSADC2 Sample Clock and SYSREF Settings ---------------------
-----------------------------------------------------------------
when x"18" => LMKRegData <= SPI_R_nW & b"000" & x"118" & CLK_DIV500M; -- Clkout6-7_odl, Clkout6-7_idl, Dclkout6_div, Table 16
when x"19" => LMKRegData <= SPI_R_nW & b"000" & x"119" & x"55"; -- Dclkout6_ddly_cnth, Dclkout6_ddly_cntl, Table 17
when x"1a" => LMKRegData <= SPI_R_nW & b"000" & x"11b" & x"01"; -- Dclkout6_adly, Dclkout6_adly_mux, Dclkout6_mux, Table 18
when x"1b" => LMKRegData <= SPI_R_nW & b"000" & x"11c" & x"00"; -- Dclkout6_hs, Sdclkout7_mux, Sdclkout7_ddly, Sdclkout7_hs, Table 19
when x"1c" => LMKRegData <= SPI_R_nW & b"000" & x"11d" & x"00"; -- Sdclkout7_adly_en, Sdclkout7_adly, Table 20
when x"1d" => LMKRegData <= SPI_R_nW & b"000" & x"11e" & CLK_EN; -- Dclkout6_ddly_pd, Dclkout6_hsg_pd, Dclkout6_adlyg_pd, Dclkout6_adly_pd, Dclkout6-7_pd, Sdclkout7_dis_mode, Sdclkout7_pd, Table 21
when x"1e" => LMKRegData <= SPI_R_nW & b"000" & x"11f" & DCLK_LVPECL; -- Sdclkout7_pol, Sdclkout7_fmt, Dclkout6_pol, Dclkout6_fmt, Table 22
-----------------------------------------------------------------
--- Spare Clock 1 and Spare SYSREF 1 Settings -------------------
-----------------------------------------------------------------
when x"1f" => LMKRegData <= SPI_R_nW & b"000" & x"120" & x"03"; -- Clkout8-9odl, Clkout8-9_idl, Dclkout8_div, Table 16
when x"20" => LMKRegData <= SPI_R_nW & b"000" & x"121" & x"55"; -- Dclkout8_ddly_cnth, Dclkout8_ddly_cntl, Table 17
when x"21" => LMKRegData <= SPI_R_nW & b"000" & x"123" & x"00"; -- Dclkout8_adly, Dclkout8_adly_mux, Dclkout8_mux, Table 18
when x"22" => LMKRegData <= SPI_R_nW & b"000" & x"124" & x"00"; -- Dclkout8_hs, Sdclkout9_mux, Sdclkout9_ddly, Sdclkout9_hs, Table 19
when x"23" => LMKRegData <= SPI_R_nW & b"000" & x"125" & x"00"; -- Sdclkout9_adly_en, Sdclkout9_adly, Table 20
when x"24" => LMKRegData <= SPI_R_nW & b"000" & x"126" & CLK_PWRDOWN; -- Dclkout8_ddly_pd, Dclkout8_hsg_pd, Dclkout8_adlyg_pd, Dclkout8_adly_pd, Dclkout8-9_pd, Sdclkout9_dis_mode, Sdclkout9_pd, Table 21
when x"25" => LMKRegData <= SPI_R_nW & b"000" & x"127" & x"00"; -- Sdclkout9_pol, Sdclkout9_fmt, Dclkout8_pol, Dclkout8_fmt, Table 22
-----------------------------------------------------------------
--- Clock Outputs Unused (No Connect) ---------------------------
-----------------------------------------------------------------
when x"26" => LMKRegData <= SPI_R_nW & b"000" & x"128" & x"03"; -- Clkout10-11_odl, Clkout10-11_idl, Dclkout10_div, Table 16
when x"27" => LMKRegData <= SPI_R_nW & b"000" & x"129" & x"55"; -- Dclkout10_ddly_cnth, Dclkout10_ddly_cntl, Table 17
when x"28" => LMKRegData <= SPI_R_nW & b"000" & x"12b" & x"00"; -- Dclkoutx_adl10, Dclkout10_adly_mux, Dclkout10_mux, Table 18
when x"29" => LMKRegData <= SPI_R_nW & b"000" & x"12c" & x"00"; -- Dclkout10_hs, Sdclkout11_mux, Sdclkout11_ddly, Sdclkout11_hs, Table 19
when x"2a" => LMKRegData <= SPI_R_nW & b"000" & x"12d" & x"00"; -- Sdclkout11_adly_en, Sdclkout11_adly, Table 20
when x"2b" => LMKRegData <= SPI_R_nW & b"000" & x"12e" & CLK_PWRDOWN; -- Dclkout10_ddly_pd, Dclkout10_hsg_pd, Dclkout10_adlyg_pd, Dclkout10_adly_pd, Dclkout10-11_pd, Sdclkout11_dis_mode, Sdclkout11_pd, Table 21
when x"2c" => LMKRegData <= SPI_R_nW & b"000" & x"12f" & x"00"; -- Sdclkout11_pol, Sdclkout11_fmt, Dclkout10_pol, Dclkout10_fmt, Table 22
-----------------------------------------------------------------
--- Transceiver Quad 1 Reference Clock and PF SYSREF1 Settings --
-----------------------------------------------------------------
when x"2d" => LMKRegData <= SPI_R_nW & b"000" & x"130" & x"03"; -- Clkout12-13_odl, Clkout12-13_idl, Dclkout12_div, Table 16
when x"2e" => LMKRegData <= SPI_R_nW & b"000" & x"131" & x"55"; -- Dclkout12_ddly_cnth, Dclkout12_ddly_cntl, Table 17
when x"2f" => LMKRegData <= SPI_R_nW & b"000" & x"133" & x"00"; -- Dclkout12_adly, Dclkout12_adly_mux, Dclkout12_mux, Table 18
when x"30" => LMKRegData <= SPI_R_nW & b"000" & x"134" & x"00"; -- Dclkout12_hs, Sdclkout13_mux, Sdclkout13_ddly, Sdclkout13_hs, Table 19
when x"31" => LMKRegData <= SPI_R_nW & b"000" & x"135" & x"00"; -- Sdclkout13_adly_en, Sdclkout13_adly, Table 20
when x"32" => LMKRegData <= SPI_R_nW & b"000" & x"136" & CLK_PWRDOWN; -- Dclkout12_ddly_pd, Dclkout12_hsg_pd, Dclkout12_adlyg_pd, Dclkout12_adly_pd, Dclkout12-13_pd, Sdclkout13_dis_mode, Sdclkout13_pd, Table 21
when x"33" => LMKRegData <= SPI_R_nW & b"000" & x"137" & x"00"; -- Sdclkout13_pol, Sdclkout13_fmt, Dclkout12_pol, Dclkout12_fmt, Table 22
-- VCO1 used for clock distribution, Oscout powered down
when x"34" => LMKRegData <= SPI_R_nW & b"000" & x"138" & x"20"; -- Vco_mux, Oscout_mux, Oscout_fmt, Table 23
-----------------------------------------------------------------
--- SYSREF Settings (Not used for JESD204B Subclass 0) ----------
-----------------------------------------------------------------
when x"35" => LMKRegData <= SPI_R_nW & b"000" & x"139" & x"00"; -- Sysref_clkin0_mux, Sysref_mux, Table 24
when x"36" => LMKRegData <= SPI_R_nW & b"000" & x"13a" & x"0c"; -- Sysref_div[12:8], Sysref_div[7:0], Table 25
when x"37" => LMKRegData <= SPI_R_nW & b"000" & x"13b" & x"00"; -- Sysref_div[12:8], Sysref_div[7:0], Table 25
when x"38" => LMKRegData <= SPI_R_nW & b"000" & x"13c" & x"00"; -- Sysref_ddly[12:8], Sysref_ddly[7:0], Table 26
when x"39" => LMKRegData <= SPI_R_nW & b"000" & x"13d" & x"08"; -- Sysref_ddly[12:8], Sysref_ddly[7:0], Table 26
when x"3a" => LMKRegData <= SPI_R_nW & b"000" & x"13e" & x"03"; -- Sysref_pulse_cnt, Table 27
-----------------------------------------------------------------
when x"3b" => LMKRegData <= SPI_R_nW & b"000" & x"13f" & x"00"; -- PLL2_nclk_mux, PLL1_nclk_mux, Fb_mux, Fb_mux_en, Table 28 *
when x"3c" => LMKRegData <= SPI_R_nW & b"000" & x"140" & x"0f"; -- PLL1_pd, Vco_ldo_pd, Vco_pd, Oscin_pd, Sysref_gbl_pd, Sysref_pd, Sysref_ddly_pd, Sysref_plsr_pd, Table 29 *
when x"3d" => LMKRegData <= SPI_R_nW & b"000" & x"141" & x"00"; -- Ddlydsysref_en, Ddlydx_en, Table 30 *
when x"3e" => LMKRegData <= SPI_R_nW & b"000" & x"142" & x"00"; -- Ddlyd_step_cnt, Table 31 *
when x"3f" => LMKRegData <= SPI_R_nW & b"000" & x"143" & x"00"; -- Sysref_clr, Sync_1shot_en, Sync_pol, Sync_en, Sync_PLL2_dld, Sync_PLL1_dld, Sync_mode, Table 32 *
when x"40" => LMKRegData <= SPI_R_nW & b"000" & x"144" & x"00"; -- Sync_dissysref, Sync_disx, Table 33 *
when x"41" => LMKRegData <= SPI_R_nW & b"000" & x"145" & x"7f"; -- Fixed Register, set to 0x7f *
when x"42" => LMKRegData <= SPI_R_nW & b"000" & x"146" & CLKIN0_EN; -- Clkin2_en, Clkin1_en, Clkin0_en, Clkin2_type, Clkin1_type, Clkin0_type, Table 37 *
when x"43" => LMKRegData <= SPI_R_nW & b"000" & x"147" & CLKIN0_PLL1; -- Clkin_sel_pol, Clkin_sel_mode, Clkin1_out_mux, Clkin0_out_mux, Table 38
when x"44" => LMKRegData <= SPI_R_nW & b"000" & x"148" & SET_LOS0; -- Clkin_sel0_mux, Clkin_sel0_type, Table 39
when x"45" => LMKRegData <= SPI_R_nW & b"000" & x"149" & SET_MISO; -- Sdio_rdbk_type, Clkin_sel1_mux, Clkin_sel1_type, Table 40
when x"46" => LMKRegData <= SPI_R_nW & b"000" & x"14a" & x"02"; -- Reset_mux, Reset_type, Table 41 *
when x"47" => LMKRegData <= SPI_R_nW & b"000" & x"14b" & x"16"; -- Los_timeout, Los_en, Track_en, Holdover_force, Man_dac_en, Man_dac[9:8], Table 42 *
when x"48" => LMKRegData <= SPI_R_nW & b"000" & x"14c" & x"00"; -- Man_dac[9:8], Man_dac[7:0], Table 43 *
when x"49" => LMKRegData <= SPI_R_nW & b"000" & x"14d" & x"00"; -- Dac_trip_low, Table 44 *
when x"4a" => LMKRegData <= SPI_R_nW & b"000" & x"14e" & x"c0"; -- Dac_clk_mult, Dac_trip_high, Table 45 *
when x"4b" => LMKRegData <= SPI_R_nW & b"000" & x"14f" & x"7f"; -- Dac_clk_cntr, Table 46 *
-----------------------------------------------------------------
--- Holdover Settings (When PLL1 Reference Clock is Lost) -------
-----------------------------------------------------------------
when x"4c" => LMKRegData <= SPI_R_nW & b"000" & x"150" & x"40"; -- Clkin_override, Holdover_PLL1_det, Holdover_los_det, Holdover_vtune_det, Holdover_hitless_switch, Holdover_en, Table 47
when x"4d" => LMKRegData <= SPI_R_nW & b"000" & x"151" & x"02"; -- Holdover_dld_cnt[13:8], Holdover_dld_cnt[7:0], Table 48
when x"4e" => LMKRegData <= SPI_R_nW & b"000" & x"152" & x"00"; -- Holdover_dld_cnt[13:8], Holdover_dld_cnt[7:0], Table 48
-----------------------------------------------------------------
------- Divider: Clock In 0 -------
-----------------------------------------------------------------
when x"4f" => LMKRegData <= SPI_R_nW & b"000" & x"153" & x"00"; -- Clkin0_r[13:8], Clkin0_r[7:0], Table 50
when x"50" => LMKRegData <= SPI_R_nW & b"000" & x"154" & x"78"; -- Clkin0_r[13:8], Clkin0_r[7:0], Table 50
-----------------------------------------------------------------
------- Divider: Clock In 1 -------
-----------------------------------------------------------------
when x"51" => LMKRegData <= SPI_R_nW & b"000" & x"155" & x"00"; -- Clkin1_r[13:8], Clkin1_r[7:0], Table 51,52
when x"52" => LMKRegData <= SPI_R_nW & b"000" & x"156" & x"78"; -- Clkin1_r[13:8], Clkin1_r[7:0], Table 51,52
-----------------------------------------------------------------
------- Divider: Clock In 2 -------
-----------------------------------------------------------------
when x"53" => LMKRegData <= SPI_R_nW & b"000" & x"157" & x"00"; -- Clkin2_r[13:8], Clkin2_r[7:0], Table 53
when x"54" => LMKRegData <= SPI_R_nW & b"000" & x"158" & x"78"; -- Clkin2_r[13:8], Clkin2_r[7:0], Table 53
-----------------------------------------------------------------
------- PLL1 Settings -------
-----------------------------------------------------------------
when x"55" => LMKRegData <= SPI_R_nW & b"000" & x"159" & x"00"; -- PLL1_n , Table 54,55
when x"56" => LMKRegData <= SPI_R_nW & b"000" & x"15a" & x"78"; -- PLL1_n , Table 54,55
when x"57" => LMKRegData <= SPI_R_nW & b"000" & x"15b" & x"d4"; -- PLL1_wnd_size, PLL1_cp_tri, PLL1_cp_pol, PLL1_cp_gain, Table 56 *
when x"58" => LMKRegData <= SPI_R_nW & b"000" & x"15c" & x"20"; -- PLL1_dld_cnt[13:8], PLL1_dld_cnt[7:0], Table 57,58
when x"59" => LMKRegData <= SPI_R_nW & b"000" & x"15d" & x"00"; -- PLL1_dld_cnt[13:8], PLL1_dld_cnt[7:0], Table 57,58
when x"5a" => LMKRegData <= SPI_R_nW & b"000" & x"15e" & x"00"; -- PLL1_r_dly, PLL1_n_dly, Table 59
-- Set PLL1 Lock Detect Output
when x"5b" => LMKRegData <= SPI_R_nW & b"000" & x"15f" & x"0B"; -- PLL1_ld_mux, PLL1_ld_type, Table 60
-----------------------------------------------------------------
------- PLL2 Settings -------
-----------------------------------------------------------------
when x"5c" => LMKRegData <= SPI_R_nW & b"000" & x"160" & x"00"; -- PLL2_r[11:8], PLL2_r[7:0], Table 61,62 *
when x"5d" => LMKRegData <= SPI_R_nW & b"000" & x"161" & x"01"; -- PLL2_r[11:8], PLL2_r[7:0], Table 61,62 *
when x"5e" => LMKRegData <= SPI_R_nW & b"000" & x"162" & x"44"; -- PLL2_p, Oscin_freq, PLL2_xtal_en, PLL2_ref_2x_en, Table 63
when x"5f" => LMKRegData <= SPI_R_nW & b"000" & x"163" & x"00"; -- PLL2_n_cal[17:0], Table 65
when x"60" => LMKRegData <= SPI_R_nW & b"000" & x"164" & x"00"; -- PLL2_n_cal[17:0], Table 65
when x"61" => LMKRegData <= SPI_R_nW & b"000" & x"165" & x"0c"; -- PLL2_n_cal[17:0], Table 65 *
-----------------------------------------------------------------
when x"62" => LMKRegData <= SPI_R_nW & b"000" & x"171" & x"aa"; -- fixed register
when x"63" => LMKRegData <= SPI_R_nW & b"000" & x"172" & x"02"; -- fixed register
when x"64" => LMKRegData <= SPI_R_nW & b"000" & x"17c" & x"15"; -- Opt_reg_1, Table 76, must be 0x15 for LMK04828 *
when x"65" => LMKRegData <= SPI_R_nW & b"000" & x"17d" & x"33"; -- Opt_reg_2, Table 77, must be 0x33 for LMK04828 *
when x"66" => LMKRegData <= SPI_R_nW & b"000" & x"166" & x"00"; -- PLL2_fcal_dis, PLL2_n, Table 67 *
when x"67" => LMKRegData <= SPI_R_nW & b"000" & x"167" & x"00"; -- PLL2_fcal_dis, PLL2_n, Table 67 *
when x"68" => LMKRegData <= SPI_R_nW & b"000" & x"168" & x"0f"; -- PLL2_fcal_dis, PLL2_n, Table 67 *
when x"69" => LMKRegData <= SPI_R_nW & b"000" & x"169" & x"59"; -- PLL2_wnd_size, PLL2_cp_gain, PLL2_cp_pol, PLL2_cp_tri, Table 68 *
when x"6a" => LMKRegData <= SPI_R_nW & b"000" & x"16a" & x"20"; -- Sysref_req_en, PLL2_dld_cnt, Table 70 *
when x"6b" => LMKRegData <= SPI_R_nW & b"000" & x"16b" & x"00"; -- Sysref_req_en, PLL2_dld_cnt, Table 70 *
when x"6c" => LMKRegData <= SPI_R_nW & b"000" & x"16c" & x"00"; -- PLL2_lf_r4, PLL2_lf_r3, Table 71 *
when x"6d" => LMKRegData <= SPI_R_nW & b"000" & x"16d" & x"00"; -- PLL2_lf_c4, PLL2_lf_c3, Table 72 *
when x"6e" => LMKRegData <= SPI_R_nW & b"000" & x"16e" & x"13"; -- PLL2_ld_mux, PLL2_ld_type, Table 73
when x"6f" => LMKRegData <= SPI_R_nW & b"000" & x"173" & x"00"; -- PLL2 Powerdown, Table 74
when x"70" => LMKRegData <= SPI_R_nW & b"001" & x"ffd" & x"00"; -- SPI lock, Table 83
when x"71" => LMKRegData <= SPI_R_nW & b"001" & x"ffe" & x"00"; -- SPI lock, Table 83
when x"72" => LMKRegData <= SPI_R_nW & b"001" & x"fff" & x"53"; -- SPI lock, Table 83
when others => LMKRegData <= (others => '0');
end case;
end process LMK_reg_proc;
