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LMK03318: LMK03318 Input Clock Duty Cycle

Pradeep Aggarwal
Prodigy 50 points
Part Number: LMK03318
Other Parts Discussed in Thread: CDCE913

I'm looking for a low jitter clock generator to generate multiple clocks ranging from 200kHz to 300MHz using a 30.72MHz input clock. Noticed that the data sheet for the above part specifies a 40 - 60% duty cycle for the input clock.

However, my 30.72MHz input clock has a 35% duty cycle. Just wondering what is dictating the 40 - 60% duty cycle and if the LMK03318 will work with 30.72MHz input clock at 35% duty cycle. If not then would be grateful if you could suggest alternative solutions.

Many thanks

  • 0
    TI__Mastermind 32575 points
    LMK03318 can accept a 35% duty cycle, but I would recommend bypassing the PLL reference doubler block, since the doubler internally generates 2x the input frequency using both + and - edges of the input clock, and this would generate large reference spurious tones on the PLL output clock.

    Regarding your desired output clock freuqnecy range: Note that LMK03318 cannot generate an output clock below ~2.4 MHz (limited by the minimum VCO frequency of 4.8 GHz, maximum post-divider value of 8, and maximum output divider value of 256).

    You could use an additional clock device, like CDCE913, to provide further clock division to get down to 200 kHz.

    Alan
  • 0 in reply to Alan O
    Prodigy 50 points
    Many thanks for your help - very helpful