Hi team,
My customer are using the CDCLVC1310. The input is the 100M crystal oscillator and output 10 different frequency clock.
But the 500M，900M and 1.6GHz output signal has high level RF radiation, can't pass the RF radiation test.
So do you have some layout recommendation about the power, GND or the output layout to reduce the RF radiation.
Can you help to share some materials about the layout for the clock buffer?
Lacey
Thanks a lot!
LVCMOS buffers are more prone to have high EMI radiation with high harmonic content due to unbalanced/single-ended signaling with high voltage swing and high edge rate (fast rise/fall time). Buffers with differential/balanced signaling with lower swing and/or slower edge rate are typically better choices for reduced EMI.
Make sure they used proper impedance matching (series termination) for good signal integrity to avoid reflections, sufficient power supply bypassing (to minimize switching transients on the supply rail), and route the clocks with controlled impedance and smallest loop area (signal and return paths). Routing clocks on inner layers with ground layers above & below can provide some shielding. Reducing the LVCMOS output swing (lower VDDO) and adding some load capacitance (reduce the edge rate) may help to reduce emissions.
Here are some resources from TI:
Alan
