We are observing TDM data (Jacinto 6 <=> Power IC) drifting issue during endurance test (devices always ON with environment variables).
It is a blocker for us now as we are going to start DV2 test and this test needs very long lead time(65days), we have to find root cause and fix it before DV2 test.
We have 14 channels so 2 TDM8 are used whereas in TDM_data2 6 slots are used. (8+6)
What we observed is :
In TDM_data2 , the data slots will drift ( xxxx xxoo => oxxx xxxo) , below pictures show a case that slots drifted by 1:
We are not sure whether TDM_data1 has such behavior or not as there a 8 slots (full).
Normal waveform:
Abnormal waveform:
some more information:
(test condition/AMP failure description from TQE, CH1/CH3/CH11/CH12/CH14 are all on TDM_data2)
