• State TI Thinks Resolved
  • Locked Locked
  • Replies 1 reply
  • Answers 1 answer
  • Subscribers 20 subscribers
  • Views 506 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

LMK03318: Abnormal output

Robin Yu
Intellectual 2190 points
Part Number: LMK03318

Hi team,

After configuration, all the output clk is as below, is it normal?

It is found that, the abnormal pulse seems happened with status0 as below.(yellow line is clk and green line is status0)

The setting is as below.

After changing the status0 output from PLL LOL to PRIREF LOS. The status0 output is really stable, but the abnormal seems the same with previous one.

Robin

  • 0
    TI__Genius 16845 points

    Hi Robin,

    The abnormal pulses on the output clock are likely due to the PLL loss of lock. When there is a pulse on PLL LOL, that means that the PLL has lost lock and the output is no longer locked to the input. This can cause the abnormal pulse on the output.

    The frequency stability of PRIREF may cause the loss of lock. If the PRIREF LOS STATUS0 waveform is stable, that indicates that the input has sufficient amplitude / slew rate, but it may not have the correct frequency. I recommend to try with a PRIREF source with greater frequency stability. You can measure the stability of the reference using a precision frequency counter.

    A PLL lock issue could also be caused by improper PLL or loop filter configuration. Can you share the config so that I may review the settings? (click File > Save)

    Kind regards,
    Lane