I’ve been using the pllatinumsim sw and I have a reference design where I set up Fosc=80Mhz, OSC_2x enabled, Fpd =160Mhz, 15mA=Icp & loop Bw ~440kHz.
The lock time requirement is <=10us!
Currently the reference design tells me that I should be able to achieve 10.7us of analog lock time (without CAL).
I’ve been working on the synth fitted on a radio prototype and I am talking through serial port.
The first SW we developed was using a “partial assist” CAL, but I’ve measured on the oscilloscope a lock time of ~ 200us stepping from 10750Mhz to 9375Mhz.
I decided to implement the “full assist” CAL but I am still far away from the lock time requirement.
Before running FCAL, I set up the registers on VCO_SEL, VCO_DACISET, VCO_CAPCTRL, PLL_N, PLL_DEN, PLL_NUM and the best lock time I got so far is now 40us.
As far as I understand the FCAL executes a calibration with two algorithms. One that ramps Vtune and an internal amplitude algorithm to optimize the phase noise.
At this stage I am not sure if this is a limit from the FCAL process or I can achieve better.
