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CDCLVD1204: Question about the PCIe Gen4 clock buffer

Vincent Li00
Intellectual 2035 points
Part Number: CDCLVD1204
Other Parts Discussed in Thread: LMK00338, LMK00334

Hi Guys

Our customer is designing new generation server product. But there some questions about the PCIe Gen4 clock selection:

1. Can the previous PCIe Gen3 clk buffer product be used as the current Gen4 100MHz clk buffer? 

2. What is the difference between PCIe Gen4 and Gen3 clk buffer? Any improve or any change? what should we pay attention about the new Gen4 product selection?

Your feedback are appreciated.

Thanks 

-Pengfei

  • 0
    TI__Mastermind 32575 points

    I would suggest LMK00334 (4-output) or LMK00338 (8-output) as PCIe clock buffers supporting up to Gen4.  These buffers contribute very small additive jitter of 0.05 ps RMS to the PCIe clock source (from clock generator or oscillator).

    The RefClk Max jitter limit is 1 ps RMS for Gen3 and 0.5 ps RMS for Gen4.

    Please see this blog which should address your questions.  The blog also mentions a couple PCIe clock generators from TI, in case you're interested in those as well.

    Timing is Everything: How to optimize clock distribution in PCIe applications
    Puneet Sareen contributed to the updates and additions to this blog in January 2018. PCI Express® (PCIe®) is an industry-leading standard input/output (I/O) technology. It is one of the most commonly…
    By in Technical articles > Analog

    Alan