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LMX2594: General informations

Part Number: LMX2594
Other Parts Discussed in Thread: PLLATINUMSIM-SW, TICSPRO-SW, TIDA-01410

Hi, I would like to ask you some information about LMX2594. Since I have not been able to find this data on the datasheet, I'd like to know:


1) the time necessary for the synthesizer to change from one output frequency to another;

2)the maximum clock speed;

3)informations about the settling time;

4) the slew-rate value for calibrated waveforms;

5) the value of the flicker noise (1/f)  at 10 kHz offset, normalized to 1 GHz, 100 MHz PFD frequency (I'd like to clarify the formula written on datasheet);

6) by using a fPD = 100 MHz, the resolution changes to 0.0235?

Thanks for your cooperation. 

  • Francesco,

    In response to your questions:

    1)  This time is equal to WriteTimeToDevice +VCOCalibrationTime+PLLAnalogSettleTime.   WriteTimeToDevice can be as fast as 3 us or so if you use 75 MHz SPI bus.   

    We show 50 us with no assist and 5 us with full assist for VCOCalibrationTime

    PLLAnalogSettleTime depends on design. 

    I encourage you to download the PLLatinumSim tool at ti.com/tool/PLLATINUMSIM-SW, which can simulate this settling time.

    2)Maximum SPI clock speed is 75 MHz

    3)See 1)

    4)  Slew rate for the output depends on the output frequency.  At higher frequencies, this looks a lot more like a sine wave.  If the output power and frequency are known, the slew rate can be calculated.  At lower frequencies, it's more like a square wave.  I don't have exact numbers for this.

    5)  For the 10 kHz normalized noise, the idea is you make a wide loop bandwidth PLL with a high phase detector frequency.  Then if you divide the output frequency to 1 GHz and look at 10 kHz offset, this will be the normalized 10 kHz noise.  Now if this was at 10 GHz and 10 kHz offset, then you subtract 20 dB to normalize this.  If it was at 1 GHz output but 1 kHz offset, then you subtract 10 dB from this number.

    6)  Our device allows exact fractions.  So for instance, if you want 1/5, you use 1/5 and you get this exact fraction.  Other devices sometimes force a large fixed fraction;  this one doesnt.

    Now if you are talking about the minimum step size, this would be:

    Fpd/Fden/CHDIV

    Fpd=100 MHz

    Fden = 1 to 2^24, so lets use 2^24

    CHDIV=1 , lets assume direct VCO frequency

    100 MHz / 2^24 = 5.96 Hz

    You can also set this up in our ticspro software at ti.com/tool/TICSPRO-SW

    Regards
    Dean

  • Thanks Dean for your precious answers. I did not understand why you take into account 24 bit instead of 32 for the divider. Can you explain in detail how the calibration operation works, and how is the 'full' mode rather than the 'partial' one applied? Thank you.
  • hi, have you received my message? In addition to what was previously requested, I would like to ask what is the maximum Slew-rate that can be reached by the board. Thank you. Greetings.
  •  Francesco,

    Here's a plot from our reference design TIDA-01410

    I see about 1.2V change in about 200 ps.

    1.2V/200ps = 6000 V/us, by my calculations.

    Actually twice that if it's differential, as this is a single-ended output.

    Regards,
    Dean

  • I need information about LMX2594 please.
    1)How much is the maximum frequency variation with respect to time, expressed in [Hz / s], when LMX2594 produces a ramp signal?
    2)I did not understand why you take into account 24 bit instead of 32 for the divider [read in the conversation above].
    3)Can you explain in detail how the calibration operation works, and how is the 'full' mode rather than the 'partial' one applied? Thank you.
  • Francesco,

    The result from the TIDA-01410 is the LMX2594 and addresses your slew rate questions. We have no maximum value, part to part variation , or temperature data on slew rate.

    1) Understand first with the ramping that the VCO will have to calibrate if you go more than about 30 MHz. You set the time and frequency of these calibrations (but you have a minimum non-zero calibration time and minimum frequency change-- 30 MHz or so) to make them more regular, but they can not be elimated. We have a plot in the datasheet that shows a broad frequency ramp that includes calibrations. You can tell the VCO to change 7.5 GHz in 1 us, but then you have to calibrate every 30 MHz for about 20 us and these calibrations put steps (predictable in time and length) and would add up to 20 us x (7500/30) = 5000 us

    Now let's say you change less than 30 us. Then you can tell the VCO to change 30 MHz in one phase detector cycle, which would be 30 MHz/0.01 us (100 MHz FPd assumed). But the issue is that the loop filter will limit this. It depends on the loop bandwidth, but I think that you couldn't do much faster than 30 MHz/us or so.

    2) The regsiters of the LMX2594 are 24 bits long, 7 address + 1 R/W, + 16 data.

    3) the datasheet gives some good description about this calibration. The basic idea is that calibration chooses the VCO core (VCO_SEL), VCO band (VCO_CAPCTRL), and VCO amplitude (VCO_DACISET). You can help the VCO by giving it a starting point, or you can do full assist, which is basically bypassing the calibration and putting in the values directly.

    Regards,
    Dean