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LMX2594: Lock time

Part Number: LMX2594
Other Parts Discussed in Thread: PLLATINUMSIM-SW

Hi, 

We're trying to work out the following about switching/programming speed.  I've used the Ti PLL tool to estimate the loop settling time, but we're not sure about the total "change frequency" time:

Q1.  How quickly can we clock in the data from a uP using the SPI bus?  How quickly can we program a full set of registers?

Q2.  How many (what subset) of the registers are needed to update the frequency (Frac-N and dividers)

Q3.  How does the VCO calibration work.  Is this automatic?  How long does it take?

Q4.  What else do we need to understand about the "change frequency" time?

As an example, suppose we wish to change from 1GHz to 10GHz, involving different Frac-N dividers, output dividers, VCOs.  How quickly will all this settle. (Approx loop BW is 350kHz)

  • Q1. How quickly can we clock in the data from a uP using the SPI bus? How quickly can we program a full set of registers?
    75 MHz is max write speed. So about 3 registers pre us. So for 112 registers, 112/3 ~ 37 us.
    But from cold power up, I would recommend programming all registers, waiting 10 ms, then reprogramming register R0 for proper calibration.

    Q2. How many (what subset) of the registers are needed to update the frequency (Frac-N and dividers)
    At least 1, FCAL_EN (R0), but also you probably will change PLL_N, and PLL_NUM. So likely 3 registers.
    But also mash_order, CHDIV, and PFD_DLY, so 6 regsiters if you have to do all these.

    Q3. How does the VCO calibration work. Is this automatic? How long does it take?
    It can be done automatcially. Datasheet says 50 us time for no assist. If you help it, you can speed up to 35 us. If you do the full assist, which is literally writing the calibration values to the device, 3 us (which is really just the SPI write time)

    Q4. What else do we need to understand about the "change frequency" time?
    This includes:
    1. SPI write Time
    2. VCO Calibration time. This includes choosing the VCO core, VCO Capcode, and VCO amplitude setting. This calburation happens automatically when register R0 is written with FCAL_EN=1
    3. Analog PLL lock time, which is loop filter dependent.

    I encourage you to try our PLLatinum Sim tool that models VCO Calibration time and analog PLL lock time at:
    ti.com/tool/PLLATINUMSIM-SW

    REgards,
    Dean