TPL5010: TPL5010 max allowed capacitance of DELAY pin

Z. LI

Part Number: TPL5010

Hi,

I want to use a P-channel mosfet for the manual reset of TPL5010. According to the datasheet this pin is sensitive to capacitance as it can affect the time setting accuracy. Could anyone tell me the max allowed capacitance ?

Thanks.

over 6 years ago

0 Arvind Sridhar over 6 years ago

TI__Mastermind 24205 points

Hi Zixun,
Let me check on this query with the applications engineer and get back to you.

0 Arvind Sridhar over 6 years ago in reply to Arvind Sridhar

TI__Mastermind 24205 points

Hi Zixun,

While we wait for additional confirmation from the applications engineer, I wanted to mention that both parasitic capacitance and leakage on the DELAY/M_DRV input pin can affect Rext reading at POR (typically 100ms measurement interval from POR). The effect of the PCB trace capacitance on the overall measurement is typically low (assuming this capacitor can be charged within a few ~ms), the impact of the leakage through the FET switch connecting/disconnecting this pin from VDD however could be much more significant and care should be taken to minimize its impact.