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Original question:

LMK03318: PDN timing and function for I2C interface

LMK03318: NO ACK

Kim Guzzino
Prodigy 170 points

Part Number: LMK03318

No ACK from any address after power cycle.

  • 0
    TI__Genius 9920 points
    Hi Kim.
    As Alan showed:
    "The suggested I2C programming procedure after power-up is:

    1. Power-up device (VDD and VDDO rails).
    2. Toggle PDN low to high.
    3. I2C read from R0. The 1st I2C transaction after power-up (either dummy read or write) should be ignored.
    4. I2C read from R0 and check for ACK or NACK.
    - If NACK is detected (due to risk of PDN startup issue in early silicon rev only), then go back from Step #2.
    - If ACK is detected, then continue to Step #5.
    5. I2C write the desired register configuration settings.
    6. If needed, toggle RESETN_SW bit to re-calibrate PLL(s)."

    Could you clarify what's the "any address"?
    Could you try I2C address 0x00? Or program to scan I2C address (for example, from 0x00 to 0xFF) for LMK03318?
    If the address is 0x00, we should go to Step #2 again.
    If the address is other one, it may be had been changed in EEPROM in some I2C abnormal R/W.

    Regards,
    Shawn
  • 0 in reply to Shawn Han
    Prodigy 170 points

    Shawn,

       I cut the trace to the PDN pin and power up. The part is responding to I2C commands now.

    Thanks.

    Kim

    close the case.

  • 0 in reply to Kim Guzzino
    TI__Genius 9920 points
    Hi Kim,
    Thanks for your update.
    To cut PDN trace is a method, an additional cap to GND would help robustness.
    Refer to datasheet "Figure 84. Recommendations for Power Up From Split-Supply Rails" & "Figure 83. Recommendations for Power Up From Single-Supply Rail".

    Normally, PDN rising transition should not be earlier than VDDO. PDN connection do not like a disturbance at power up stage.
    When the disturbance happened, set correct GPIO logic, toggle PDN again to initial chip.

    Regards,
    Shawn