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Original question:

CDCE913: Requirements for a crystal connected to CDCE913

CDCE913: Pulling range measured in actual board was different from that calculated by suggested expression.

user5859459
Prodigy 110 points
Part Number: CDCE913


e2e.ti.com/.../2757988

In above thread, I heard that a pulling range of CDCE913 can be calculated by following expression.

  Pullability (ppm/pF) = C1 * 1e6 / [2 * (C0 + CL)^2 ]
  Pulling Range (ppm) = Pullability * CL

So, I selected a below crystal.

  CL: 8 pF
  C0: 1.3 pF
  C1: 5.08 fF
  -> Pullability = 29.4 (ppm/pF)
     Pulling Range = 235 (ppm)

Then I replaced the crystal on our board with it, and I measured pulling range.
(How I measured it is described in above thread.)
As a result, the pulling range of it was 133ppm.
It is quite a bit different from the calculated value.

[1st question]
I think that "parasitic board capacitance" might affect the result mainly.
Is this thought correct?
If there are any other factor affecting the result, please tell me.

[2nd question]
If it affects the result, where should the value of it be inserted in the above expression?
  ex) Pullability (ppm/pF) = C1 * 1e6 / [2 * (C0 + CL + Cpar)^2 ]
      (Cpar: parasitic board capacitance)

[3rd question]
Why the displayed unit of "Crystal" in "Pulling Range Plot" of "TI Clock Pro" is "fF" ?
In above thread, I heard that the "Crystal" means "Load Capacitance" of a target crystal.
If so, I think that the unit should be "pF".


Best Regards

  • 0
    TI__Mastermind 32575 points
    1. Yes, Cpar could be the issue.
    2. I don't think so. A crystal's pullability is an intrinsic parameter defined by the crystal's internal specs alone (C0, C1, CL_target), and it does not include the "effective" or actual load cap seen by the crystal (Con-chip + Cpar). The actual pullability will be lower than the crystal's intrinsic pullability due non-idealities/mismatch in the actual load cap and parasitics.
    3. Yes, that is a typo - it should be "pF" as you stated.

    Alan
  • 0 in reply to Alan O
    Prodigy 110 points

    Thank you!
    Question 1 and question 3 were resolved.


    > A crystal's pullability is an intrinsic parameter defined by the crystal's internal specs alone (C0, C1, CL_target),
    > and it does not include the "effective" or actual load cap seen by the crystal (Con-chip + Cpar).

    I am sorry for my poor knowledge.
    What is "Con-chip" ?
    Is this what Timothy T mentioned in previous thread ? >> "Note CDCE913 adds ~1.5 pF capacitance intrinsically."
    e2e.ti.com/.../2741913


    > The actual pullability will be lower than the crystal's intrinsic pullability due non-idealities/mismatch in the actual load cap and parasitics.

    If the crystal is the widest pulling range calculated by above expression, is it actually the widest pulling range too?
    I'd like to know how to calculate a pullability where Cpar (and Con-chip) is considered.
    Because I'd like to know whether our crystal selection are most optimized or not.


    Best Regards

  • 0 in reply to user5859459
    TI__Mastermind 32575 points
    CLon-chip = CL1*CL2 / (CL1+CL2) is discussed in section 3.2 of SCAA085A. It is the on-chip variable capacitor (varactor) which is tuned by Vctrl pin.

    Pull Range (ppm) = C1/2 * (CLmax - CLmin) / ((C0 + CLmax)*(C0 +CLmin)) * 1e6
    where
    - CLmax and CLmin are the maximum and minimum load cap that can be presented to the crystal.
    - CLmin = CLon-chip@Vctrl_min + Cpar
    - CLmax = CLon-chip@Vctrl_max + Cpar

    Recall from my previous thread reply: e2e.ti.com/.../2757988
    "For Crystal 1, the center target CL is 8 pF. The change in the Vctrl is translated in a variation of the varactor value from its center target CL value (8 pF) to the corners of 2.4 pF (0.3 x 8 pF) and 10.4 pF (1.3 x 8 pF) for a total delta of 8 pF. "
    In the above case for Crystal 1 (CL_target = 8 pF):
    - CLon-chip@Vctrl_min = 2.4 pF
    - CLon-chip@Vctrl_max = 10.4 pF

    I believe I have helped all I can on this subject.

    Alan
  • 0 in reply to Alan O
    Prodigy 110 points

    > CLon-chip

    I had misunderstood that it meant "con" "chip".
    Thank you!


    > Pull Range (ppm) = C1/2 * (CLmax - CLmin) / ((C0 + CLmax)*(C0 +CLmin)) * 1e6
    > where
    > - CLmax and CLmin are the maximum and minimum load cap that can be presented to the crystal.
    > - CLmin = CLon-chip@Vctrl_min + Cpar
    > - CLmax = CLon-chip@Vctrl_max + Cpar

    Assigning 5 pF to Cpar in this expression as a test, the calculated value and the actual value are almost same.
    We will check the actual value of Cpar.
    Thank you for your kindly help!

    Best Regards