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LMK00301: Digital data buffer

Lacey Lin
Intellectual 2900 points

Part Number: LMK00301

Hi team，

I notice the LMK00301 only can support the duty cycle from 40% to 60%.

My customer want to know if the LMK00301 can buffer the digital data which has the random number of 1 or 0 data.

So the duty cycle is not fix. The voltage level is the CML.

If the LMK00301 can't support this, does any other clock buffer can support?

Lacey

Thanks a lot!

  • 0
    TI__Mastermind 32575 points

    Please see thus thread.

    What is the incoming data rate?

    The output duty cycle spec is input duty cycle +/- 5% (not +/-10% as you stated).

    Alan

  • 0 in reply to Alan O
    TI__Intellectual 2900 points
    Hi Alan,
    The incoming data is the OC-3 data, it about 150Mbps.
    Just to confirm one thing, the output signal duty cycle is +/- 5% of input signal duty cycle-----it is supported in all duty cycle input or just 50% duty cycle input?

    Lacey
    Thanks a lot!
  • 0 in reply to Lacey Lin
    TI__Genius 9920 points
    Hi Lacey,
    This clock buffer do not have duty cycle calibration function, so the output signal duty cycle would follow input signal duty cycle.
    The 45%~55%duty cycle specification is ensured by characterization and is not tested in production. So user should measure the output signal for OC-3 data fanout.
    Notice here REFout can't be used, because it is a synchronized output, period trigger signal is not available for a data stream.

    Regards,
    Shawn